Here's the first CPU-Z validation of AMD's 12-core Magny Cours processor. Whatever details the existing version of CPU-Z does read, perfectly matches the specifications of the processor sketched out so far. Firstly, it's based on AMD's upcoming socket G3 package that marks Opteron's transition to high-level integration within a single package. With 1,974 pins, socket G3 is able to provide as many as six 16-bit HyperTransport 3.1 links, and four DDR3 memory channels. The package is one of AMD's first multi-chip modules, that houses two six-core dies (dubbed "nodes"), onto one package, and connects the two using a HyperTransport link.

Each node has 6 x 512 KB of L2 cache and 6 MB L3 cache shared between the six cores. Out of 6 MB, 1 MB of the cache is reserved for low-level system operations, namely the HT Assist (probe filter) that aims to lower memory subsystem latencies, reduces queuing delays due to lower HyperTransport traffic overhead, and minimizes probe traffic to increase system bandwidth. The CPU-Z reading of 10 MB total chip L3 cache is spot-on. Also seen on the validation page are details on the reference motherboard, called "AMD Dinar", that uses SR5690 (same chip as 890FX) + SB750 chipset. The CPU-Z validation can be found here.