Derek12and now says I have PCIe 1.1 which is true

W1zzardbefore it showed "@ x16", now it shows "@ x16 1.1", kinda the same thing but easier to understand. It looked especially weird with "PCI-E x16 3.0 @ x16"

btarunrIt fixes a bug related to "APIC counter broken" on AMD Fusion APU platforms.

MabanHere comes the flood of angry Fermi owners.

kaktus1907unfortunately it breaks GTX460 pixelfillrate

www.abload.de/img/desktop_2011_12_20_20przhk.png

MabanIt doesn't break it, it fixes it. Fermi pixel fillrate is more based on the SM count than the ROP count for Fermi. (I don't know why, it just is.) You can read about it in this thread: www.techpowerup.com/forums/showthread.php?t=155459


Basically fillrate = core clock x SMs x 2.

kaktus1907Yes, It is if there is no MSAA as i said.. when you use MSAA all ROPs are available.. because MSAA doesnt increase the amount of data to be transmitted between the SMs and ROPs..

MabanI'd like to see info on that worded in such a way my head wouldn't explode from reading it. (Supertired Maban is supertired)

GooglishWe were also able to learn more about limiting the fillrate of GF100 and GF104 to share it. It is at the level of communication between the SMs and ROPs which is limited to 64 bits per cycle. Thus, traditional rendering, each SM can output two pixels per cycle or 32 in total for the GF100 and 16 in total for the GF104. Whether the first to be equipped with 48 ROPs and the second 32 ROPs, the limit will be 32 and 16 pixels per cycle. The rasterizers also offer the same speed. We could say that the ROPs are slower in rendering FP16 (64 bits per pixel) and FP32 (128 bits per pixel), they will all be able to help with these reports. But it is not because, again, the datapath between the SMs and ROPs is limited to 64 bits. We do not know if this is a limitation due from the beginning by Nvidia, s it is a compromise made ​​short drive or a backup set up following a problem. Nevertheless we believe it is an important limitation of the architecture that prevents the full benefit of all ROPs and to a lesser extent the available memory bandwidth. Consolation prize, the ROPs "useless" are involved when antiliasing is used as the filter increases the load on the ROPs without increasing the amount of data to be transmitted between the SMs and ROPs.

DrunkenMafiaIt says tested on 7970.... come on w1zz can you pm me some benchies... :) I won't share em, promise!!

btarunrHold your horses for another...24 hours.

Derek12hmmm Intel GMA 3150 wasn't fixed.

W1zzardwhats the problem? also post a screenshot please