The HyperTransport Consortium released an updated specification, HT 3.1, that increases the base clock speed of the HyperTransport bus from its previous version 3.0 limit of 2600 MHz (5200 MT/s) to 3200 MHz (6400 MT/s). The upcoming 45nm processors will be given a host of architectural updates, one of them being a revised HT 3.1 system bus. Since AMD processors use a 32-bit wide HyperTransport link to the core logic, the aggregate bandwidth of the system but would be raised to 51.6 GB/s (25.8 GB/s in each direction).

This 10 GB/s increment is supposed to favour the upcoming AMD Fusion processors, where a graphics processor would be embedded into the CPU. That could also mean that the CPU could carry PCI-Express switches, effectively eradicating the northbridge. This would mean performance gains with the CPU communicating with PCI-E devices directly instead of through a northbridge-based PCI-E switch, much in the same way as integration of memory controllers five years ago helped AMD processors. It is expected that motherboard vendors have no problems implementing HT 3.1, the AMD 790GX and 790FX chipsets offer native support to HT 3.1 with 45 nm CPUs.