In my experience, reducing polling rate or raising refresh rate solves the problem.
For those who are not having problems, you can reduce the refresh rate to 120-60Hz, you should notice the problem and a change in the extent of the problem.
There is one reliable explanation why Zen4 gets a solid boost from AVX-512. This is because x86 arch. x86 is a fossil trash.
x86 decoders cannot saturate execution units with operations to execute, and using SIMD with longer vector register gives a boost because it requires less commands to decode.
Eth mining ends on 19th sep. The next day, GPU manufacturer introduces a new arch, that has a solid advantage over the cards of the mining era.
It looks like NVidia is planning to cut all used cards from market and maintain its market share.
1-2. How can AESE/MC pair discard the fact that the recent x86 cannot issue more than one AESENC?
Two RISC instructions per one AES round are irrelevant. ARM A78 can decode four, ARM X1 can take five, IBM Power9 can chaw eight. And nobody can give guarantee that ARM will (not) implement fused...
Wait. But you can issue 128-bit instruction four times and if you have four 128-bit ALU you get the same result. There is no need to extend an ISA, if an ISA is modern and effective. ARM can issue 4 vector instructions, but x86 can't. It's explains why ancient architecture becomes more ugly...