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Recent content by AlB80

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    GPU-Z and CPU-Z window "rubberbanding"

    Nice. I had it on win10 with amd/intel igpu. Did nvidia fix that?
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    GPU-Z and CPU-Z window "rubberbanding"

    Ubuntu or Win? I have never encountered such a problem with Ubuntu, but it appeared with the win10/1kHz/60Hz combination.
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    GPU-Z and CPU-Z window "rubberbanding"

    In my experience, reducing polling rate or raising refresh rate solves the problem. For those who are not having problems, you can reduce the refresh rate to 120-60Hz, you should notice the problem and a change in the extent of the problem.
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    GPU-Z and CPU-Z window "rubberbanding"

    This problem involves monitor refresh rate too. It looks like some kind of animation is tied to both rates.
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    AMD Ryzen 7040 Series Phoenix APUs Surprisingly Performant with AVX-512 Workloads

    There is one reliable explanation why Zen4 gets a solid boost from AVX-512. This is because x86 arch. x86 is a fossil trash. x86 decoders cannot saturate execution units with operations to execute, and using SIMD with longer vector register gives a boost because it requires less commands to decode.
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    NVIDIA CEO Confirms RTX 40-series "Ada" Reveal in September, Launch Aimed at Not Cannibalizing "Ampere"

    Eth mining ends on 19th sep. The next day, GPU manufacturer introduces a new arch, that has a solid advantage over the cards of the mining era. It looks like NVidia is planning to cut all used cards from market and maintain its market share.
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    AMD Radeon Software Adrenalin 21.11.2 Released

    Nice joke.
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    AMD Ryzen 7 5700G

    What about "Scan Converters" and "Packers"? Or did the author want to leave us in the dark?
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    Intel Launches 10nm "Tiger Lake" Desktop Processors

    There is "Vertical Segment: Desktop" at your link now.
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    AMD "Zen 4" Microarchitecture to Support AVX-512

    1-2. How can AESE/MC pair discard the fact that the recent x86 cannot issue more than one AESENC? Two RISC instructions per one AES round are irrelevant. ARM A78 can decode four, ARM X1 can take five, IBM Power9 can chaw eight. And nobody can give guarantee that ARM will (not) implement fused...
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    AMD "Zen 4" Microarchitecture to Support AVX-512

    Wait. But you can issue 128-bit instruction four times and if you have four 128-bit ALU you get the same result. There is no need to extend an ISA, if an ISA is modern and effective. ARM can issue 4 vector instructions, but x86 can't. It's explains why ancient architecture becomes more ugly...
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    AMD "Zen 4" Microarchitecture to Support AVX-512

    Are Intel Pentiums or Celerons every CPU? f.e. latest Pentium G6600 (LGA1200).
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    AMD "Zen 4" Microarchitecture to Support AVX-512

    I hope they didn't put 512bit vector ALU.
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    Need moar power? LX-3600W PSU

    AC Input 180V * 10A = 1800W After applying 90 PLUS Platitum standard (90% consumed by PSU. It explains why this PSU so big) we can get up to 180W.
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