With PowerVia, Intel Achieves a Chipmaking Breakthrough

[trieste15]

“The benefits of this approach are manifold,…”

I had to laugh when I read this. I believe they meant “many fold”. Otherwise cool stuff!

Manifold is correct

Definition of MANIFOLD

marked by diversity or variety; many; comprehending or uniting various features : multifarious… See the full definition

www.merriam-webster.com

 

[hs4]

Thanks for the clarification. I'm not very hopeful about that timeline. It seems way too aggressive given that even Meteor Lake hasn't started shipping.

A positive assessment of Intel's plan would be that their stagnation in the FinFET era was due to the choice of metal layer material (cobalt wiring), while the silicon processing technology itself was doing well. Recently, they finally found a suitable material and got a fine metal pitch of 30-36 nm, almost equivalent to TSMC N3E. PowerVIA's technology to alleviate metal layer crowding will enable high density at 20A/18A with the same pitch as Intel 4/3.

Metal layer miniaturization has been a recent struggle for TSMC as well, and N3 failed to do so, leading to N3E with wider metal pitch, which has delayed 3nm volume production by 2 years.

Intel's recent 1-2 year delay is also due to the European lockdown caused by COVID-19, which stalled EUV lithography equipment production and delayed the delivering. Instead, it appears that Intel has acquired much of the next generation EUV lithography equipment to be delivered after 2024.

 

[AnotherReader]

A positive assessment of Intel's plan would be that their stagnation in the FinFET era was due to the choice of metal layer material (cobalt wiring), while the silicon processing technology itself was doing well. Recently, they finally found a suitable material and got a fine metal pitch of 30-36 nm, almost equivalent to TSMC N3E. PowerVIA's technology to alleviate metal layer crowding will enable high density at 20A/18A with the same pitch as Intel 4/3.

Metal layer miniaturization has been a recent struggle for TSMC as well, and N3 failed to do so, leading to N3E with wider metal pitch, which has delayed 3nm volume production by 2 years.

Intel's recent 1-2 year delay is also due to the European lockdown caused by COVID-19, which stalled EUV lithography equipment production and delayed the delivering. Instead, it appears that Intel has acquired much of the next generation EUV lithography equipment to be delivered after 2024.

Intel 4 still uses a combination of tantalum and cobalt for the barriers and liners that surround the wires. This is also Intel's first process that will use EUV and TSMC has substantial experience with EUV in production so I wouldn't discount them just yet. Intel also had problems with its 14 nm process before they ever went to Cobalt. I hope they hit their targets, because TSMC needs competition, but based on the past, I'm cautiously pessimistic.