Sandy Bridge block diagram

[qubit]

I'm trying to find a block diagram for Sandy Bridge, but I can't find one. In particular, I want one that shows how they've implemented the various bits in each core. I'm curious if it has a full FPU per core and if it supports Hyper Threading. I'd also be on the lookout for anything else interesting in this diagram.

I don't need this for any special reason other than geeky curiousity (which I'm sure all my friends on here will totally relate to ) since I have a Sandy 2700K.

And before anyone tells me to jfgi, I've already done some frantic googling, including limiting it to intel.com but come up with nothing useful.

 

[Norton]

Will this help???

http://www.realworldtech.com/sandy-bridge/3/

 

[Aquinus]

Intel's execution pipeline hasn't changed a whole lot from the C2D, since the memory controller has moved to the CPU on Nehelem, it's safe to assume anything used on skt1366, 1156, 1155, and 2011 is going to be about the same. Intel isn't going to release anything too specific about their cores and what they do to make them go fast, but you may be looking for something like this.

This is a bit out of the pipeline for nehelem, it really hasn't change too much but maybe you can find something on SB, but it shouldn't be too far off.

Edit: Aha, I think you want this: http://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf

I think this might be what you wanted:

I've actually never taken the time to look at this. Makes a lot of sense why Intel can run single threads really quickly. There isn't much for shared components, each instruction must execute pretty quickly.