Intel's Process Roadmap Gets Updated with Plans to go Back to Two Year Cadence
During the IEDM event hosted by the IEEE organization, ASML's CEO, Martin van den Brink, took the stage to elaborate more on ASML's vision of the future of semiconductors. When talking about the future of semiconductors, Mr. Brink started talking about Intel and their vision for the future. Intel's slides were showing many things including backporting of IP to older processes and plan to go back to "tick-tock" two-year cadence to restore the previous confidence in Intel's manufacturing capabilities.
Perhaps one of the most interesting notes about the presentation is the fact that Intel is working hard to realize its plans of bringing back a two-year cadence of "tick-tock" process realization. That means that in the future, presumably after 10 nm debut problems are solved, Intel wants to do the old process and optimization tactics. A slide (shown below) titled "In Moore We Trust" is speaking a lot about Intel's future plans, showing few things in particular: Intel's upcoming 10 nm++ and 10 nm+++ nodes, and the possibility of backporting.
Perhaps one of the most interesting notes about the presentation is the fact that Intel is working hard to realize its plans of bringing back a two-year cadence of "tick-tock" process realization. That means that in the future, presumably after 10 nm debut problems are solved, Intel wants to do the old process and optimization tactics. A slide (shown below) titled "In Moore We Trust" is speaking a lot about Intel's future plans, showing few things in particular: Intel's upcoming 10 nm++ and 10 nm+++ nodes, and the possibility of backporting.