Phison Electronics, a leading provider of NAND controllers and storage solutions, today announced aiDAPTIV+ partnerships with ASUS, Gigabyte, MAINGEAR, and MediaTek. At GTC 2024, Phison and partners will demonstrate aiDAPTIV+, a hybrid hardware and software large language model (LLMs) fine-tune training solution that enables small and medium-sized businesses (SMBs) to process and retain local control of their sensitive machine learning (ML) data.

Foundational training of LLMs gives a broad understanding of language but aiDAPTIV+ enables the fine-tuning process that molds these models into specialized tools capable of understanding the topics that deliver precise results for your business needs. Commodity workstation hardware is enhanced with aiDAPTIV+ software, and first generation aiDAPTIVCache Series ai100 SSDs to enable larger training models than previously possible in a workstation form-factor.

Alphawave Semi (LSE: AWE), a global leader in high-speed connectivity for the world's technology infrastructure, today announced successful collaboration with Keysight Technologies, a market-leading design, emulation, and test solutions provider, demonstrating interoperability between Alphawave Semi's PCIe 6.0 64 GT/s Subsystem (PHY and Controller) Device and Keysight PCIe 6.0 64 GT/s Protocol Exerciser, negotiating a link to the maximum PCIe 6.0 data rate. Alphawave Semi, already on the PCI-SIG 5.0 Integrators list, is accelerating next-generation PCIe 6.0 Compliance Testing through this collaboration.

Alphawave Semi's leading-edge silicon implementation of the new PCIe 6.0 64 GT/s Flow Control Unit (FLIT)-based protocol enables higher data rates for hyperscale and data infrastructure applications. Keysight and Alphawave Semi achieved another milestone by successfully establishing a CXL 2.0 link setting the stage for future cache coherency in the datacenter.

Phison Electronics, a global leader in NAND controllers and storage solutions, announced today that the company has expanded its portfolio of PCIe 5.0 high-speed transmission solutions with PCIe 5.0, CXL 2.0 compatible redriver and retimer data signal conditioning IC products. Leveraging the company's deep expertise in PCIe engineering, Phison is the only signal conditioners provider that offers the widest portfolio of multi-channel PCIe 5.0 redriver and retimer solutions and PCIe 5.0 storage solutions designed specifically to meet the data infrastructure demands of artificial intelligence and machine learning (AI+ML), edge computing, high-performance computing, and other data-intensive, next-gen applications. At the 2023 Open Compute Project Global Summit, the Phison team is showcasing its expansive PCIe 5.0 portfolio, demonstrating the redriver and retimer technologies alongside other enterprise NAND flash, illustrating a holistic vision for a PCIe 5.0 data ecosystem to address the most demanding applications of the AI-everywhere era.

"Phison has focused industry-leading R&D efforts on developing in-house, chip-to-chip communication technologies since the introduction of the PCIe 3.0 protocol, with PCIe 4.0 and PCIe 5.0 solutions now in mass production, and PCIe 6.0 solutions now in the design phase," said Michael Wu, President & General Manager, Phison US. "Phison's accumulated experience in high-speed signaling enables our team to deliver retimer and redriver design solutions that are optimized for top signal integration, low power usage, and high temperature endurance, to deliver interface speeds for the most challenging compute environments."

Intel at the 2023 InnovatiON event unveiled a 288-core extreme core-count variant of the Xeon "Sierra Forest" processor for high-density servers for scale-out, cloud-native environments. It succeeds the current 144-core model. "Sierra Forest" is a server processor based entirely on efficiency cores, or E-cores, based on the "Sierra Glen" core microarchitecture, a server-grade derivative of "Crestmont," Intel's second-generation E-core that's making a client debut with "Meteor Lake."

Xeon "Sierra Forest" is a chiplet-based processor, much like "Meteor Lake" and the upcoming "Emerald Rapids" server processor. It features a total of five tiles—two Compute tiles, two I/O tiles, and a base tile (interposer). Each of the two Compute tiles is built on the Intel 3 foundry node, a more advanced node than Intel 4, featuring higher-density libraries, and an undisclosed performance/Watt increase. Each tile has 36 "Sierra Glen" E-core clusters, 108 MB of shared L3 cache, 6-channel (12 sub-channel) DDR5 memory controllers, and Foveros tile-to-tile interfaces.

Lightelligence, the global leader in photonic computing and connectivity systems, today announced Photowave, the first optical communications hardware designed for PCIe and Compute Express Link (CXL) connectivity, unleashing next-generation workload efficiency.

Photowave, an Optical Networking (oNET) transceiver leveraging the significant latency and energy efficiency of photonics technology, empowers data center managers to scale resources within or across server racks. The first public demonstration of Photowave will be at Flash Memory Summit today through Thursday, August 10, in Santa Clara, Calif.

Micron Technology, Inc. (Nasdaq: MU), today announced sample availability of the Micron CZ120 memory expansion modules to customers and partners. The Micron CZ120 modules come in 128 GB and 256 GB capacities in the E3.S 2T form factor, which uses PCIe Gen 5 x8 interface. Additionally, the CZ120 modules are capable of running up to 36 GB/s memory read/write bandwidth and augment standard server systems when incremental memory capacity and bandwidth is required. The CZ120 modules use Compute Express Link (CXL) standards and fully support the CXL 2.0 Type 3 standard. By leveraging a unique dual-channel memory architecture and Micron's high-volume production DRAM process, the Micron CZ120 delivers higher module capacity and increased bandwidth. Workloads that benefit from more memory capacity include AI training and inference models, SaaS applications, in-memory databases, high-performance computing and general-purpose compute workloads that run on a hypervisor on premise or in the cloud.

"Micron is advancing the adoption of CXL memory with this CZ120 sampling milestone to key customers," commented Siva Makineni, vice president of the Micron Advanced Memory Systems Group. "We have been developing and testing our CZ120 memory expansion modules utilizing both Intel and AMD platforms capable of supporting the CXL standard. Our product innovation coupled with our collaborative efforts with the CXL ecosystem will enable faster acceptance of this new standard, as we work collectively to meet the ever-growing demands of data centers and their memory-intensive workloads."

Samsung Electronics, a world leader in advanced semiconductor technology, today announced its development of the industry's first 128-gigabyte (GB) DRAM to support Compute Express Link (CXL) 2.0. Samsung worked closely with Intel on this landmark advancement on an Intel Xeon platform.

Building on its development of the industry's first CXL 1.1-based CXL DRAM in May of 2022, Samsung's introduction of the 128 GB CXL DRAM based on CXL 2.0 is expected to accelerate commercialization of next-generation memory solutions. The new CXL DRAM supports PCle 5.0 interface (x8 lanes) and provides bandwidth of up to 35 GB per second.

Montage Technology, a leading data processing and interconnect IC design company, announced today that its PCIe 5.0/CXL 2.0 Retimer has successfully achieved mass production. This chip is a key upgrade based on Montage's PCIe 4.0 Retimer, providing a stable and reliable PCIe 5.0 and CXL 2.0 interconnect solution with high bandwidth and low latency for the cloud and high-performance computing market.

Montage's PCIe 5.0/CXL 2.0 Retimer employs advanced signal conditioning technologies to improve signal integrity and increase the effective transmission distance of high-speed signals. Compliant with relevant PCI-SIG and CXL specifications, the chip meets mainstream package requirements, supports transfer rate up to 32 GT/s, and takes the lead in supporting ultra-low transmission latency of less than 5 ns. The chip supports various complex system topologies such as SRIS and Retimer cascading, offering an ideal solution to address the PCIe/CXL signal integrity challenges in next-generation servers, enterprise storage, and AI acceleration systems. The PCIe 5.0/CXL 2.0 Retimer has passed extensive interoperability testing with a variety of compute, storage and networking products, such as CPU, PCIe switches, SSDs, GPUs and NICs, thus laying a solid foundation for the large-scale deployment of cloud computing and data centers.

Phison Electronics Corp., a global leader in NAND flash controller and storage solutions, today is demonstrating the company's latest PCIe Gen5 innovation that is transcending system-level performance to new heights at CES in Las Vegas. Phison is demonstrating the E26 with Phison's proprietary I/O+ Technology to usher a new evolution of gaming experiences. For enterprise, Phison is previewing the company's latest Gen5 X Series SSD enterprise controllers, which can provide twice the performance per watt (in comparison to X1, the previous generation). Following the success of the world's first PCI-SIG Association certified PCIe 5.0 Redriver PS7101, Phison is also introducing the PS7201 Retimer with industry-proven IP. Phison's Retimer is designed to solve performance and data integrity issues in enterprise and automotive applications and further enhances the Gen5 ecosystem.

"Phison is ecstatic to be ringing in the new year by showcasing our product milestones for the industry, our partners and enterprise customers because we are committed and dedicated to engineering next generation technologies through ecosystem excellence," said Michael Wu, GM & President of Phison Technology Inc. (USA). "As a proven category leader, Phison's E26 with I/O+ Technology, latest Enterprise PCIe Gen5 X Series, signal enhancing Redriver and Retimer are product breakthroughs that are a testament to our engineering success."

SMART Modular Technologies, Inc. a global leader in memory solutions, solid-state drives, and hybrid storage products announces its new Compute Express Link (CXL) Memory Module, the XMM CXL memory module. SMART's new DDR5 XMM CXL modules helps boost server and data center performance by enabling cache coherent memory to be added behind the CXL interface, further expanding big data processing capabilities beyond the current 8-channel/12-channel limitations of most servers.

The industry adoption of composable serial-attached memory architecture enables a whole new era for the memory module industry. Serial-attached memory adds capacity and bandwidth capabilities beyond main memory DIMM modules. Servers with XMM CXL modules can be dynamically configured for different applications and workloads without being shut down. Memory can be shared across nodes to meet throughput and latency requirements.

According to TrendForce research, material supply improvement and spiking demand for enterprise SSDs from North American hyperscale data center and enterprise clients in 2Q22 coupled with the Kioxia contamination incident in 1Q22 prompted customers to ramp up procurement to avoid future supply shortages. Manufacturers also give priority to meeting the needs of server customers due to the high pricing of enterprise SSD. In the second quarter, overall revenue of the enterprise SSD market increased by 31.3% to US$7.32 billion.

As the market leader, Samsung has grown its enterprise SSD revenue to US$3.26 billion with the recovery of enterprise SSD procurement. Especially in the second quarter, when orders for other consumer products continued to decline, enterprise SSD became the company's outlet for reducing production capacity. At present, Samsung has been continuously investing in the development of next-generation transmission specification products such as the CXL 2.0 product released at the Flash Summit in early August, in order to maintain a leading position in the market.

SMART Modular Technologies, Inc. ("SMART"), a division of SGH and a global leader in memory solutions, solid-state drives, and hybrid storage announces its new Compute Express Link (CXL) Memory Module, the XMM CXL memory module. SMART's new DDR5 XMM CXL modules helps boost server and data center performance by enabling cache coherent memory to be added behind the CXL interface, further expanding big data processing capabilities beyond the current 8-channel/12-channel limitations of most servers.

The industry adoption of composable serial-attached memory architecture enables a whole new era for the memory module industry. Serial-attached memory adds capacity and bandwidth capabilities beyond main memory DIMM modules. Servers with XMM CXL modules can be dynamically configured for different applications and workloads without being shut down. Memory can be shared across nodes to meet throughput and latency requirements.

The CXL Consortium, an industry standards body dedicated to advancing Compute Express Link (CXL) technology, today announced the release of the CXL 3.0 specification. The CXL 3.0 specification expands on previous technology generations to increase scalability and to optimize system level flows with advanced switching and fabric capabilities, efficient peer-to-peer communications, and fine-grained resource sharing across multiple compute domains.

"Modern datacenters require heterogenous and composable architectures to support compute intensive workloads for applications such as Artificial Intelligence and Machine Learning - and we continue to evolve CXL technology to meet industry requirements," said Siamak Tavallaei, president, CXL Consortium. "Developed by our dedicated technical workgroup members, the CXL 3.0 specification will enable new usage models in composable disaggregated infrastructure."

Montage Technology, a leading data processing and interconnect IC design company, today announced that it has delivered the world's first Compute Express Link (CXL ) Memory eXpander Controller (MXC). The device is designed to be used in Add-in Cards (AIC), Backplanes or EDSFF memory modules to enable significant scaling of memory capacity and bandwidth for data-intensive applications such as high-performance computing (HPC) and artificial intelligence (AI). The MXC is a Type 3 CXL DRAM memory controller. The MXC supports and is compliant with both DDR4 & DDR5 JEDEC standards. It is also designed to the CXL 2.0 specification and supports PCIe 5.0 specification speeds. The MXC provides high-bandwidth and low-latency interconnect between the CPU and the CXL-based devices, allowing them to share memory for higher performance, reduced software stack complexity, and lower data center TCO.

Montage Technology's President, Stephen Tai said, "CXL is a key technology that enables innovative ways to do memory expansion and pooling which will play an important role in next-generation server platforms. I'm very excited that Montage is the first company in the industry to successfully deliver the MXC chip, which signals we are making a critical step towards advancing the CXL interconnect technology to the memory market." CXL Consortium's President, Siamak Tavallaei said, "The CXL Consortium is excited to see continued CXL specification adoption to enable technologies and solutions such as the CXL DRAM Memory eXpander Controller." Montage Technology is working closely with industry-leading memory manufacturers to deliver advanced memory products based on the CXL MXC and help develop a robust memory ecosystem around CXL.

The CXL Consortium, an industry standards body dedicated to advancing Compute Express Link (CXL) technology, today announced the release of the CXL 2.0 specification. CXL is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices. The CXL 2.0 specification adds support for switching for fan-out to connect to more devices; memory pooling for increased memory utilization efficiency and providing memory capacity on demand; and support for persistent memory - all while preserving industry investments by supporting full backwards compatibility with CXL 1.1 and 1.0.

"Datacenter architectures continue to evolve rapidly to support the growing demands of emerging workloads for Artificial Intelligence and Machine Learning, with CXL technology keeping pace to meet the performance and latency demands," said Barry McAuliffe, president, CXL Consortium. "Designed with breakthrough performance and easy adoption as guiding principles, the CXL 2.0 specification is a significant achievement from our dedicated technical work group members."