AMD today announced the expansion of the AMD Versal adaptive system on chip (SoC) portfolio with the new Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 adaptive SoCs, which bring preprocessing, AI inference, and postprocessing together in a single device for end-to-end acceleration of AI-driven embedded systems.

These initial devices in the Versal Series Gen 2 portfolio build on the first generation with powerful new AI Engines expected to deliver up to 3x higher TOPs-per-watt than first generation Versal AI Edge Series devicesi, while new high-performance integrated Arm CPUs are expected to offer up to 10x more scalar compute than first gen Versal AI Edge and Prime series devicesii.

At Embedded World 2024, Enclustra will showcase limitless potential to innovate the next big thing with over 20 FPGA (Field Programmable Gate Array) embedded system on module (SoM) technology solutions. Starting with unveiling Pluto, its tiny titan at 30 x 30 mm, the new coin-sized SoM with the strength of AMD Zynq UltraScale+ MPSoC, features ultra-compact embedded intelligence and portability, accelerating development of compact and portable low-power applications in industrial, healthcare, and security. Pluto's miniature form factor and high processing power are ideal for real-time video processing in medical smart glasses, VR, environmental monitoring, drones, autonomous navigation, and artificial intelligence inference.

"Enclustra leverages strategic partnerships with AMD, Altera and Microchip to provide customers with a comprehensive ecosystem of cutting-edge FPGA solutions optimized for performance and cost. We integrated their technology into our Pluto SoM, enabling unparalleled processing power and efficiency in a compact form factor," said Philipp Baechtold, CEO of Enclustra GmbH. "The future is bright for innovation with FPGA embedded chip technologies, creating life-saving, life-changing, and dream-making solutions."

AEWIN provides a series of performant Network Appliances and Edge Server powered by single AMD Zen 4c EPYC 8004 processor codenamed Siena. The latest AMD Siena CPU is produced with 5 nm manufacturing technology to have up to 64 cores (extreme density of 2CCX/CCD) and 225 W TDP with lower energy consumption compared to EPYC SP5. Siena SP6 CPU has the best performance per watt and is with the support of rich I/O and CXL 1.1.

SCB-1945 (1U) and SCB-1947A (2U) are two performant Network Appliances supporting 12x DDR5 sockets and 4x/8x PCIe Gen 5 slots for AEWIN self-design NICs with 1G to 100G copper/fiber interfaces (with/without bypass function) or other accelerators and NVMe SSDs. Both models provide the flexibility to change 2x front panel PCIe slots to 1x PCIe x16 slot for installing off-the-shelf add-on card for additional functions required. It can support 400G NIC card installed such as NVIDIA Mellanox PCIe 5.0 NIC.

Yesterday, AMD announced that its cutting-edge adaptive computing technology was selected by Sony Semiconductor Solutions (SSS) for its newest automotive LiDAR reference design. SSS, a global leader in image sensor technology, and AMD joined forces to deliver a powerful and efficient LiDAR solution for use in autonomous vehicles. Using adaptive computing technology from AMD significantly extends the SSS LiDAR system capabilities, offering extraordinary accuracy, fast data processing, and high reliability for next-generation autonomous driving solutions.

In the rapidly evolving landscape of autonomous driving, the demand for precise and reliable sensor technology has never been greater. LiDAR (Light Detection and Ranging) technology plays a pivotal role in enabling depth perception and environmental mapping for various industries. LiDAR delivers image classification, segmentation, and object detection data that is essential for 3D vision perception enhanced by AI, which cannot be provided by cameras alone, especially in low-light or inclement weather. The dedicated LiDAR reference design addresses the complexities of autonomous vehicle development with a standardized platform to enhance safety in navigating diverse driving scenarios.

During its 55th annual shareholders' meeting, Samsung Electronics announced its entry into the AI processor market with the upcoming launch of its Mach-1 AI accelerator chips in early 2025. The South Korean tech giant revealed its plans to compete with established players like NVIDIA in the rapidly growing AI hardware sector. The Mach-1 generation of chips is an application-specific integrated circuit (ASIC) design equipped with LPDDR memory that is envisioned to excel in edge computing applications. While Samsung does not aim to directly rival NVIDIA's ultra-high-end AI solutions like the H100, B100, or B200, the company's strategy focuses on carving out a niche in the market by offering unique features and performance enhancements at the edge, where low power and efficient computing is what matters the most.

According to SeDaily, the Mach-1 chips boast a groundbreaking feature that significantly reduces memory bandwidth requirements for inference to approximately 0.125x compared to existing designs, which is an 87.5% reduction. This innovation could give Samsung a competitive edge in terms of efficiency and cost-effectiveness. As the demand for AI-powered devices and services continues to soar, Samsung's foray into the AI chip market is expected to intensify competition and drive innovation in the industry. While NVIDIA currently holds a dominant position, Samsung's cutting-edge technology and access to advanced semiconductor manufacturing nodes could make it a formidable contender. The Mach-1 has been field-verified on an FPGA, while the final design is currently going through a physical design for SoC, which includes placement, routing, and other layout optimizations.

AMD today announced the AMD Spartan UltraScale+ FPGA family, the newest addition to the extensive portfolio of AMD Cost-Optimized FPGAs and adaptive SoCs. Delivering cost and power-efficient performance for a wide range of I/O-intensive applications at the edge, Spartan UltraScale+ devices offer the industry's highest I/O to logic cell ratio in FPGAs built in 28 nm and lower process technology, deliver up to 30 percent lower total power consumption versus the previous generation, and contain the most robust set of security features in the AMD Cost-Optimized Portfolio.

"For over 25 years the Spartan FPGA family has helped power some of humanity's finest achievements, from lifesaving automated defibrillators to the CERN particle accelerator advancing the boundaries of human knowledge," said Kirk Saban, corporate vice president, Adaptive and Embedded Computing Group, AMD. "Building on proven 16 nm technology, the Spartan UltraScale+ family's enhanced security and features, common design tools, and long product lifecycles further strengthen our market-leading FPGA portfolio and underscore our commitment to delivering cost-optimized products for customers."

Intel announced today that it is reviving the Altera brand name for its new standalone FPGA (field-programmable gate array) company. The business was previously known as Intel's Programmable Solutions Group before being spun off into an independent entity two months ago. The chipmaking giant acquired Altera in 2015 for $16.7 billion to bolster its FPGA capabilities. Using the well-known Altera moniker for the new standalone company signals Intel's confidence in the FPGA market opportunity, which it estimates to be over $55 billion across data centers, communications, and embedded segments. As a standalone company with its own board of directors, Altera will be able to focus exclusively on the FPGA market. Intel will remain a majority shareholder, but outside investment could help fund expansion plans.

Altera plans to build on the Programmable Solutions Group's recent efforts targeting lower-end and mid-range FPGAs for embedded devices in industrial, automotive and aerospace/defense applications. According to Intel CEO Pat Gelsinger, independence will give Altera "the mandate, focus and resources to better capitalize on the attractive expected growth of FPGAs." The revival of the Altera brand and refocus on the FPGA market comes alongside Intel's plan to invest heavily in new chip factories and advanced manufacturing capabilities. With Altera as a standalone business, Intel aims to be a significant player in the expected high growth of the global FPGA industry. Alongside new naming, Altera is introducing Agilex 9, which is now in volume production; Agilex 7 F-series and I-series released to production; Agilex 5 now broadly available, and Agilex 3 coming soon, with functions for cloud, communications and intelligent edge applications. Below, you can see the specification table of the upcoming FPGAs.

Tachyum today announced that it has added a Performance Monitoring Unit (PMU) to its Prodigy FPGA emulation system, empowering customers and partners with the ability to address bottlenecks and better optimize Prodigy performance for all applications and workloads. The PMU is an essential tool for collecting information about performance bottlenecks. It offers the ability to record a wide range of events that encompass every aspect of the Prodigy Universal Processor without slowing down the application itself. Tools like perf then present this information after the application is finished, enabling the identification and characterization of performance bottlenecks that may exist in the processor core, full mesh interconnect fabric, memory, and I/O subsystems. Perf is a go-to instrument for everybody working on performance assessment and tuning under Linux. The PMU's wide range of performance counters - supported by both software C-model and FPGA - facilitates both system debugging and performance tuning.

Tachyum's PMU enables faster time to market by allowing customers and partners to quickly identify performance issues and rapidly converge to a solution for all phases of go-to-market, including evaluation, development and final production testing. It provides an invaluable tool suite for customers spanning a broad array of markets, including AI, HPC and cloud computing.

AMD has quietly issued a product discontinuation notice—their PDF document is dated January 1 2024—for a whole bunch of Xilinx Complex Programmable Logic Device (CLPD) and lower-end FPGA models. Team Red's opening statement on the matter reads: "AMD will be discontinuing XC9500XL, CoolRunner XPLA 3, CoolRunner II, Spartan II, and Spartan 3, 3A, 3AN, 3E, 3ADSP Commercial/ Industrial "XC" and Automotive "XA" Product Families due to declining run-rate and supplier sustainability reasons." The American multinational semiconductor inherited a large back catalog of programmable logic products once their acquisition of Xilinx was completed back in 2022.

Industry analysts believed that this takeover was mainly motivated by a desire to expand into FPGA territories, although Team Red indicated that it would carry on producing and supporting Xilinx's older CLPD products—for example, the Spartan 3 family debuted back in 2011, while a couple of the CoolRunner II parts on the list are of 2002 vintage. AMD's discontinuation notice provides details of Last Time Buy (LTB) final orders—the cut-off date for soon-to-be-axed devices appears to be June 29 2024.

Naver, the firm behind the HyperCLOVA X large language model (LLM), has been working with Samsung Electronics toward the development of power-efficient AI accelerators. The collaboration brings Naver's expertise with Samsung's vast systems IP over silicon design, the ability to build complex SoCs, semiconductor fabrication, and its plethora of DRAM technologies. The two recently designed a proof of concept for an upcoming AI chip, which they iterated on an FPGA. Naver claims the AI chip it is co-developing with Samsung will be 8 times more energy efficient than an NVIDIA H100 AI accelerator, but did not elaborate on its actual throughput. Its solution, among other things, leverages energy-efficient LPDDR memory from Samsung. The two companies have been working on this project since December 2022.

Ayar Labs, a leader in silicon photonics for chip-to-chip connectivity, will showcase its in-package optical I/O solution integrated with Intel's industry-leading Agilex Field-Programmable Gate Array (FPGA) technology. In demonstrating 5x current industry bandwidth at 5x lower power and 20x lower latency, the optical FPGA - packaged in a common PCIe card form factor - has the potential to transform the high performance computing (HPC) landscape for data-intensive workloads such as generative artificial intelligence (AI), machine learning, and support novel new disaggregated compute and memory architectures and more.

"We're on the cusp of a new era in high performance computing as optical I/O becomes a 'must have' building block for meeting the exponentially growing, data-intensive demands of emerging technologies like generative AI," said Charles Wuischpard, CEO of Ayar Labs. "Showcasing the integration of Ayar Labs' silicon photonics and Intel's cutting-edge FPGA technology at Supercomputing is a concrete demonstration that optical I/O has the maturity and manufacturability needed to meet these critical demands."

BeagleBoard.org, a pioneer in open-source single-board computers (SBCs), is excited to unveil the BeagleV -Fire, a revolutionary SBC powered by the Microchip's PolarFire MPFS025T FCVG484E 5x core RISC-V System on Chip (SoC) with FPGA fabric. This remarkable addition to the BeagleBoard.org BeagleV family of boards opens up new horizons for developers, tinkerers, and the open-source community to explore the vast potential of RISC-V architecture and FPGA technology.

BeagleV -Fire is the second board in the BeagleV series of single board computers (SBCs) from BeagleBoard.org. BeagleV -Fire like other BeagleV SBCs, is set to revolutionize the world of embedded systems and empower developers and enthusiasts worldwide. After the launch of BeagleV -Ahead, BeagleV -Fire represents another significant milestone in the democratization of computer architecture and open-source hardware development for the masses. Built around the powerful and energy-efficient RISC-V instruction set architecture (ISA) along with its versatile FPGA fabric, BeagleV -Fire SBC offers unparalleled opportunities for developers, hobbyists, and researchers to explore and experiment with RISC-V technology.

Zero ASIC, a semiconductor startup, came out of stealth today to announce early access to its one-of-a-kind ChipMaker platform, demonstrating a number of world firsts:

• 3D chiplet composability enabling billions of new silicon products
• Fully automated no-code chiplet-based chip design
• Zero install interactive RTL-based chip emulation
• Roadmap to 100X reduction in chip development costs

"Custom Application Specific Integrated Circuits (ASICs) offer 10-100X cost and energy advantage over commercial off the shelf (COTS) devices, but the enormous development cost makes ASICs non-viable for most applications," said Andreas Olofsson, CEO and founder of Zero ASIC. "To build the next wave of world changing silicon devices, we need to reduce the barrier to ASICs by orders of magnitude. Our mission at Zero ASIC is to make ordering an ASIC as easy as ordering catalog parts from an electronics distributor."

Phison Electronics, a global leader in NAND controllers and storage solutions, announced today that the company has expanded its portfolio of PCIe 5.0 high-speed transmission solutions with PCIe 5.0, CXL 2.0 compatible redriver and retimer data signal conditioning IC products. Leveraging the company's deep expertise in PCIe engineering, Phison is the only signal conditioners provider that offers the widest portfolio of multi-channel PCIe 5.0 redriver and retimer solutions and PCIe 5.0 storage solutions designed specifically to meet the data infrastructure demands of artificial intelligence and machine learning (AI+ML), edge computing, high-performance computing, and other data-intensive, next-gen applications. At the 2023 Open Compute Project Global Summit, the Phison team is showcasing its expansive PCIe 5.0 portfolio, demonstrating the redriver and retimer technologies alongside other enterprise NAND flash, illustrating a holistic vision for a PCIe 5.0 data ecosystem to address the most demanding applications of the AI-everywhere era.

"Phison has focused industry-leading R&D efforts on developing in-house, chip-to-chip communication technologies since the introduction of the PCIe 3.0 protocol, with PCIe 4.0 and PCIe 5.0 solutions now in mass production, and PCIe 6.0 solutions now in the design phase," said Michael Wu, President & General Manager, Phison US. "Phison's accumulated experience in high-speed signaling enables our team to deliver retimer and redriver design solutions that are optimized for top signal integration, low power usage, and high temperature endurance, to deliver interface speeds for the most challenging compute environments."

ASUS, a global infrastructure solution provider, is excited to announce its participation in the 2023 OCP Global Summit, which is taking place from October 17-19, 2023, at the San Jose McEnery Convention Center. The prestigious annual event brings together industry leaders, innovators and decision-makers from around the world to explore and discuss the latest advancements in open infrastructure and cloud technologies, providing a perfect stage for ASUS to unveil its latest cutting-edge products.

The ASUS theme for the OCP Global Summit is Solutions beyond limits—ASUS empowers AI, cloud, telco and more. We will showcase an array of products:

Intel Corporation today announced its intent to separate its Programmable Solutions Group (PSG) operations into a standalone business. This will give PSG the autonomy and flexibility it needs to fully accelerate its growth and more effectively compete in the FPGA industry, which serves a broad array of markets, including the data center, communications, industrial, automotive, aerospace and defense sectors. Intel also announced that Sandra Rivera, executive vice president at Intel, will assume leadership of PSG as chief executive officer; Shannon Poulin has been named chief operating officer.

Standalone operations for PSG are expected to begin Jan. 1, 2024, with ongoing support from Intel. Intel expects to report PSG as a separate business unit when it releases first-quarter 2024 financials. Over the next two to three years, Intel intends to conduct an IPO for PSG and may explore opportunities with private investors to accelerate the business's growth, with Intel retaining a majority stake.

AMD today announced the AMD Alveo UL3524 accelerator card, a new fintech accelerator designed for ultra-low latency electronic trading applications. Already deployed by leading trading firms and enabling multiple solution partner offerings, the Alveo UL3524 provides proprietary traders, market makers, hedge funds, brokerages, and exchanges with a state-of-the-art FPGA platform for electronic trading at nanosecond (ns) speed.

The Alveo UL3524 delivers a 7X latency improvement over prior generation FPGA technology, achieving less than 3ns FPGA transceiver latency for accelerated trade execution. Powered by a custom 16 nm Virtex UltraScale + FPGA, it features a novel transceiver architecture with hardened, optimized network connectivity cores to achieve breakthrough performance. By combining hardware flexibility with ultra-low latency networking on a production platform, the Alveo UL3524 enables faster design closure and deployment compared to traditional FPGA alternatives.

AMD today announced AMD Kria K24 System-on-Module (SOM) and KD240 Drives Starter Kit, the latest additions to the Kria portfolio of adaptive SOMs and developer kits. AMD Kria K24 SOM offers power-efficient compute in a small form factor and targets cost-sensitive industrial and commercial edge applications. Advanced InFO (Integrated Fan-Out) packaging makes the K24 half the size of a credit card while using half the power of the larger, connector-compatible Kria K26 SOM.

The K24 SOM provides high determinism and low latency for powering electric drives and motor controllers used in compute-intensive digital signal processing (DSP) applications at the edge. Key applications include electric motor systems, robotics for factory automation, power generation, public transportation such as elevators and trains, surgical robotics and medical equipment like MRI beds, and EV charging stations. Coupled with the KD240 Drives Starter Kit, an out-of-the-box-ready motor control-based development platform, the products offer a seamless path to production deployment with the K24 SOM. Users can quickly be up and running, speeding time to market for motor control and DSP applications without requiring FPGA programming expertise.

To address customers' growing needs, Intel expanded its Intel Agilex FPGA portfolio and broadened its Programmable Solutions Group (PSG) offerings to handle the increased demand for customized workloads, including enhanced AI capabilities, and to provide lower total cost of ownership (TCO) and more complete solutions. These new products and technologies will be the focus of Intel's FPGA Technology Day (IFTD) on Sept. 18, where hardware engineers, software developers and system architects can interact with Intel and partner experts.

FPGAs play an important role in Intel's portfolio by offering flexible and customizable platform capabilities for demanding applications and workloads. Intel FPGAs solve customer challenges from cloud to edge with AI capabilities across silicon, IP and software. Intel's latest announcements illustrate how the company's increased investment in its FPGA portfolio is unfolding. So far in 2023, Intel has released 11 of 15 expected new products - more new product introductions than ever in Intel's FPGA business. As disclosed in its second quarter 2023 earnings call, Intel reported that its PSG business unit delivered 35% revenue growth year-over-year, marking the third consecutive quarter of record revenue.

QuickLogic Corporation, a developer of embedded FPGA (eFPGA) IP, ruggedized FPGAs and Endpoint AI/ML solutions, and YorChip, a pioneering startup specializing in UCIe-compatible IP, have formed a strategic partnership to revolutionize the world of FPGA chiplets. The collaboration will result in a groundbreaking lineup of FPGA chiplets optimized for low power consumption and low cost, opening new possibilities for a wide range of applications, including the fast-growing edge IoT and AI/ML markets.

According to Yole Group, a market research company, by 2023, they expect chiplet adoption will lead to a TAM of chiplet-based integrated circuits in excess of $200B, across the consumer, automotive defense, aerospace, industrial, and medical markets. Since discrete FPGAs are already prevalent in those same markets, wide adoption of eFPGA-based UCIe (Unified Chiplet Interconnect Express) enabled chiplets is expected, and QuickLogic and YorChip are well-positioned to capitalize on this growth opportunity.

At this year's Hot Chips event, Intel provided the first in-depth look at its next-generation Intel Xeon product lineup, built on a new, innovative platform architecture. The platform marks an important evolution for Intel Xeon by introducing processors with a new Efficient-core (E-core) architecture alongside its well-established Performance-core (P-core) architecture. Code-named Sierra Forest and Granite Rapids, respectively, these new products will bring simplicity and flexibility to customers, offering a compatible hardware architecture and shared software stack to tackle critical workloads such as artificial intelligence.

"It is an exciting time for Intel and its Xeon roadmap. We recently shipped our millionth 4th Gen Xeon, our 5th Gen Xeon (code-named Emerald Rapids) will launch in Q4 2023 and our 2024 portfolio of data center products will prove to be a force in the industry," said Lisa Spelman, Intel corporate vice president and general manager of Xeon Products and Solutions.

OpenHW Group today announced that the industry's most comprehensive Development Kit for an open-source RISC-V MCU is now available to be ordered. The OpenHW CORE-V MCU DevKit includes an open-source printed circuit board (PCB) which integrates OpenHW's CORE-V MCU and various peripherals, a software development kit (SDK) with a full-featured Eclipse-based integrated development environment (IDE), as well as connectivity to Amazon Web Services (AWS) via AWS IoT ExpressLink for secure and reliable connectivity between IoT devices and AWS cloud services.

The comprehensive open-source CORE-V MCU DevKit enables software development for embedded, internet-of-things (IoT), and artificial intelligence (AI)-driven applications. The CORE-V MCU is based on the open-source CV32E40P embedded-class processor, a small, efficient, 32-bit, in-order open-source RISC-V core with a four-stage pipeline that implements the RV32IM[F]C RISC-V instruction extensions.

Magewell today announced two new models in the company's Eco Capture family of ultra-compact, power-efficient M.2 video capture cards. Hot on the heels of the recently introduced Eco Capture AIO M.2—which features selectable HDMI and SDI 1080p60 inputs—the Eco Capture HDMI 4K Plus M.2 and Eco Capture 12G SDI 4K Plus M.2 capture 4K video at 60 frames per second over HDMI or SDI interfaces, respectively. Magewell will highlight the new Eco Capture models alongside other innovations in stand 7.A44 at the IBC 2023 exhibition in Amsterdam from September 15 to 18.

Magewell's Eco Capture cards offer systems integrators and OEM developers a space-efficient, high-performance video capture solution with low latency and low power consumption. Ideal for use in small, portable or embedded systems where full-sized PCIe slots are not available, the cards feature an M.2 connector and measure only 22 mm x 80 mm (0.87x3.15 in). The new models are the first Eco Capture cards to leverage a PCIe Gen 3 bus interface, offering increased DMA bandwidth over earlier siblings.

AMD today announced revenue for the second quarter of 2023 of $5.4 billion, gross margin of 46%, operating loss of $20 million, net income of $27 million and diluted earnings per share of $0.02. On a non-GAAP basis, gross margin was 50%, operating income was $1.1 billion, net income was $948 million and diluted earnings per share was $0.58.

"We delivered strong results in the second quarter as 4th Gen EPYC and Ryzen 7000 processors ramped significantly," said AMD Chair and CEO Dr. Lisa Su. "Our AI engagements increased by more than seven times in the quarter as multiple customers initiated or expanded programs supporting future deployments of Instinct accelerators at scale. We made strong progress meeting key hardware and software milestones to address the growing customer pull for our data center AI solutions and are on-track to launch and ramp production of MI300 accelerators in the fourth quarter."

Introducing the Versal HBM Series VHK158 Evaluation Kit. This features the Versal HBM series VH1582 device, which integrates multi-Tbps High Bandwidth Memory (HBM), hardened connectivity IP, and adaptive compute in a single device, eliminating the bottlenecks between memory, I/O, and compute while delivering up to 6 times more memory bandwidth.

The VHK158 evaluation kit is an evaluation platform for the Versal HBM series VH1582 device designed to keep up with the higher memory needs of compute intensive, memory bound applications, providing adaptable acceleration for data center, wired networking, test & measurement, and aerospace & defense applications. The VHK158 board's primary focus is to enable demonstration and evaluation of the VH1582 silicon and support customer application development