Teledyne LeCroy, the worldwide leader in serial data test solutions is pleased to announce that the Peripheral Component Interconnect Special Interest Group (PCI-SIG), responsible for the definition of serial expansion buses and related components required to drive fast, efficient transfers between processors and peripheral devices, has approved Teledyne LeCroy as a solution vendor for official PCI Express (PCIe ) 5.0 link and transaction layer compliance testing at the PCI-SIG compliance workshops.

Compliance testing allows design and test engineers to ensure product interoperability as well as adherence to the PCIe standard, enabling technology adoption among integrators. The Summit Z58 Protocol Exerciser/Analyzer which was previously approved for PCIe 3.0 and 4.0 compliance testing has now also been approved for official PCIe 5.0 compliance and certification testing, making it the only piece of test equipment currently certified for link and transaction layer testing of all three PCIe generations. Passing the PCI-SIG's compliance tests are also a necessary step for equipment to be included in the PCI-SIG's Integrators List.

Tektronix, Inc., introduces the industry's first PCI Express 6.0 compatible Base transmitter test solution just weeks after the PCI-SIG working group released PCI Express (PCIe) 6.0 Base specifications and validation requirements. PCIe 6.0 is an important and scalable standard for data-intensive markets such as data center, artificial intelligence/machine learning (AI/ML), and high-performance computing. To meet ever growing performance demands, PCIe 6.0 standard transitions to PAM4 signaling and new innovative error correcting techniques. The Tektronix test solution includes PCIe 6.0 measurement-specific software, enhanced PAM4 DSP capabilities and noise compensation on the oscilloscope for increased accuracy of results. The Tektronix test solution for PCIe 6.0 standard is further enhanced by the industry-leading analysis tools for SNDR and uncorrelated jitter measurements which are both mandated requirements for the PCIe 6.0 standard.

The industry's first PCIe 6.0 standard transmitter validation solution is focused on serving high-performance and data-intensive markets and is available worldwide for use with DPO70000SX ATI Performance Oscilloscopes. "Tektronix' PCIe 6.0 standard test solution came to market quickly because of the company's deep involvement in the PCI-SIG working group, where it helped define the standard's measurement methodologies," said David Bouse, PCI Express Principal Technology Lead at Tektronix and PCI-SIG working group participant.

As you're most likely aware of, NVIDIA introduced a new power connector with its RTX 30-series Founders Edition graphics cards and at the time it was something of a controversy, especially as none of its AIB partners went for the connector. As it turned out, the connector was largely accepted by the PCI-SIG, with a few additions which lead to the 12VHPWR connector. The main difference between the two was the addition of a small set of sense connectors, for a 12+4-pin type connector. It has now been confirmed that the 12VHPWR will work with NVIDIA's Founders Edition cards, although this isn't a huge surprise as such, but rather good news for those that happen to own a Founders Edition card and are looking to invest in a new PSU.

However, what's more interesting in the news about the 12VHPWR connector is that it will operate in two distinct modes. If the 4-pin sense connector isn't connected to the GPU, the PSU will only deliver 450 Watts to the GPU, presumably as some kind of safety precaution. On the other hand, if the sense connector is used, the same cable can deliver up to 600 Watts, which would allow for a combined card power draw of up to 675 Watts for next generation GPUs. It's possible that we'll see cards with multiple power thresholds that will be negotiated on the fly with the PSU and we might also see PSU's that can force a lower power state of the GPU in case the overall system load gets too high. It'll be interesting to see what the new standard delivers, since so far not a lot of details have been released with regards to how the sense function works in detail.

PCI-SIG, the organization responsible for the widely adopted PCI Express (PCIe ) standard, today announced the official release of the PCIe 6.0 specification, reaching 64 GT/s. PCI Express technology has served as the de facto interconnect of choice for nearly two decades. The PCIe 6.0 specification doubles the bandwidth and power efficiency of the PCIe 5.0 specification (32 GT/s), while providing low latency and reduced bandwidth overhead.

"PCI-SIG is pleased to announce the release of the PCIe 6.0 specification less than three years after the PCIe 5.0 specification," said Al Yanes, PCI-SIG Chairperson and President. "PCIe 6.0 technology is the cost-effective and scalable interconnect solution that will continue to impact data-intensive markets like data center, artificial intelligence/machine learning, HPC, automotive, IoT, and military/aerospace, while also protecting industry investments by maintaining backwards compatibility with all previous generations of PCIe technology."

Western Digital is preparing to update its client SSD lineup with a new flagship product, the WD Black SN850X. The drive was referenced in a December 10 certification filing with the PCI-SIG. The drive unsurprisingly features a PCI-Express 4.0 x4 interface. Nothing else is known about the drive, but the "X" in its name could signify a performance uplift over the current WD Black SN850 from an updated controller, a newer generation of NAND flash, or better stock cooling. Interestingly, the listing also references a drive called "SN820," which could be an "unbranded" successor to the PC SN810, a drive the company sells to system integrators and OEMs.

The upcoming graphics cards based on PCIe Gen5 standard will utilize the latest PCIe connector with double bandwidth of the previous Gen4 that we use today and bring a new power connector that the next generation of GPUs brings. According to the information exclusive to Igor's Lab, the new connector will be called the 12VHPWR and will carry as many as 16 pins with it. The reason it is called 12VHPWR is that it features 12 pins for power, while the remaining four are signal transmission connectors to coordinate the delivery. This power connector is supposed to carry as much as 600 Watts of power with its 16 pins.

The new 12VHPWR connector should work exclusively with PCIe Gen5 graphics cards and not be backward compatible with anything else. It is said to replace three standard 8-pin power connectors found on some high-end graphics cards and will likely result in power supply manufacturers adopting the new standard. The official PCI-SIG specification defines each pin capable of sustaining up to 9.2 Amps, translating to a total of 55.2 Amps at 12 Volts. Theoretically, this translates to 662 Watts; however, Igor's Lab notes that the connector is limited to 600 Watts. Additionally, the 12VHPWR connector power pins have a 3.00 mm pitch, while the contacts in a legacy 2×3 (6-pin) and 2×4 (8-pin) connector lie on a larger 4.20 mm pitch.

Back in June of 2019, the PCI-SIG announced that work had started on PCIe 6.0 and some two years and four months later, PCIe 6.0 has reached version 0.9, which equals draft spec. What this means is that companies can now start to implement PCIe 6.0 into their products, to make sure they're compliant with the draft spec, since no additional functional changes will be made, unless something major is discovered.

PCIe 6.0 will be the first PCIe standard to use PAM-4 encoding, something it shares with GDDR6 memory among other standards. What this means is that twice the data can be sent per clock cycle for 64GT/s, or twice that of PCIe 5.0. Another key feature is FEC or low-latency forward error correction, as this was implemented to maintain data integrity. PCIe 6.0 is expected to be backwards compatible with all previous versions of PCIe. The final PCIe 6.0 spec isn't likely to be finalised until early next year, based on previous standards, although the original plan was to finish ratifying the spec this year.

At the COMPUTEX 2021 Virtual Expo in May, TEAMGROUP presented the core value underlying its new products in 2021: "Chill the Heat, Feel the Speed, Make it Big", representing cooling, DDR5, and large capacity, the three major focuses TEAMGROUP builds its new products and design concepts around. Tonight at 10 PM (GMT+8), everyone is sincerely invited to the TEAMGROUP Online Launch Event 2021 via official website, Facebook Page, and YouTube channel as it again takes the three focuses to the next level with its powerful new technical capabilities and innovative technologies. To celebrate the event with the world, TEAMGROUP will give away a Gaming Desktop PC and other prizes worth up to $7,000 USD. Make sure to stay tuned for the TEAMGROUP Online Launch Event 2021.

In recent years, TEAMGROUP has been focusing on developing diverse cooling solutions and applying unique materials to the SSD of the Gaming product line, T-FORCE. Inspired by the four natural elements of wind, fire, water, and earth, TEAMGROUP has utilized four exclusive components of cooling to T-FORCE gaming products. The wind element can be found in TEAMGROUP's CARDEA A440 Pro M.2 PCIe SSD as further improvements are made on existing aluminium fin thermal conductivity technology for fluid ventilation and more effective cooling performance. The impressive read/write speeds of the CARDEA A440 Pro are also approaching the defined maximum speeds for Gen4 x4 by PCI-SIG at an outstanding 7,400/7,000 MB/s.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD233: XFM Embedded and Removable Memory Device (XFMD) standard. XFMD (XFM stands for Crossover Flash Memory) is a new universal data storage media providing an NVMe over PCI Express interface in a small, thin form factor. The device is designed to bring replaceable storage to devices typically soldered down in IoT devices and embedded applications. Developed by JEDEC's JC-64.1 Subcommittee for Electrical Specifications and Command Protocols, JESD233 is available for download from the JEDEC website.

JESD233 XFMD is a removable, versatile memory solution intended for use in a wide range of applications that require an easy device exchange. Examples include IoT devices, automotive applications, notebook PCs, gaming consoles, video recording devices (drones, surveillance systems, etc.), Extended Reality (AR, VR, MR), and more.

To maximize connectivity between the host and the device, JESD233 XFMD leverages industry-leading standards from PCI-SIG and NVM Express, Inc. The PCI Express interface provides fundamental bus connectivity and NVM Express serves as the higher level protocol for accessing the non-volatile media as a low-latency logical storage device.

TechPowerUp today released the latest version of TechPowerUp GPU-Z, the popular graphics subsystem information and monitoring utility. With the latest version 2.38.0, we are introducing the ability to detect Resizable BAR support. GPU-Z can now tell whether Resizable BAR is supported, and if so, whether it is enabled. AMD refers to Resizable BAR as AMD Smart Access Memory, but it is a feature developed by the PCI-SIG, which lets your CPU see the entire video memory of your discrete graphics card as a single addressable block, rather than through 256 MB apertures. This feature has been found to improve performance in games that can take advantage of it. Resizable BAR status can now be viewed from the main tab, right next to the multi-GPU status.

The latest TechPowerUp GPU-Z also adds support for new and upcoming GPUs, including AMD Radeon RX 6700 XT, RX 6700, RX 6600 XT, RX 6600, and Ryzen "Lucienne" mobile processor iGPUs. Support is also added for NVIDIA GeForce RTX 3070 Mobile. Other new features include the ability to monitor negative temperatures on NVIDIA GPUs. We fixed video BIOS extraction on AMD RDNA2 GPUs (Radeon RX 6000 series). Grab GPU-Z from the link below.

DOWNLOAD: TechPowerUp GPU-Z 2.38.0The change-log follows.

AMD in its "Where Gaming Begins Episode 3" online event, announced that it is introducing Smart Access Memory (resizable base address register) support to Ryzen 3000 series "Matisse" processors, based on the "Zen 2" microarchitecture. These exclude the Ryzen 3 3200G and Ryzen 5 3400G. The PCI-SIG innovated feature was, until now, restricted to the Ryzen 5000 series on the AMD platform, although is heavily proliferated across the Intel platform. Resizable BAR enables the CPU to see the graphics card's entire dedicated memory as one addressable block, rather than through 256-megabyte apertures. For game engines that are able to take advantage of the feature, this could translate to a performance boost of up to 16 percent. Be on the lookout for BIOS updates from your motherboard manufacturer.

NVIDIA on Tuesday announced a roll-out of its implementation of the PCI-SIG resizable base-address register (BAR) feature to select GeForce products. The feature enables your CPU to see the entire video memory of your graphics card as one addressable block, rather than through 256 MB apertures. This should improve certain kinds of 3D rendering workloads, and game engines that are optimized to use it should see a tangible performance boost. AMD earlier introduced the exact same feature under its marketing name "Smart Access Memory," with its Radeon RX 6000 series.

NVIDIA announced that resizable-BAR support will be made available to GeForce RTX 30-series "Ampere" desktop graphics cards, notebooks that have RTX 30-series "Ampere" mobile GPUs, and future products. The support requires not just a compatible graphics card, but also a motherboard that supports the feature. Most leading motherboard- and OEM desktop manufacturers began rolling out resizable-BAR support through UEFI firmware updates. Using the feature requires you to run your machine in native UEFI mode (with CSM disabled).

PCI-SIG has recently confirmed that version 0.7 of the PCIe 6.0 Specification has been officially released to its members. The PCI-SIG organization has already ratified the PCIe 5.0 standard and plans to release the full PCIe 6.0 specification in 2021. PCIe 6.0 will bring the same doubling in data rates seen with previous generations of the standard including a 2x improvement over PCIe 5.0, 4x boost over PCIe 4.0, and an 8x increase in speeds over the common PCIe 3.0 standard.

The organization has been speeding up its timeline for new versions of the PCIe specification with PCIe 3.0 being released in 2010 followed by PCIe 4.0 in 2017, PCIe 5.0 in 2019, and with PCIe 6.0 expected in 2021. The PCIe 6.0 standard is designed to fulfill the needs of future devices in the PC and enterprise markets such as 800 Gb/s Ethernet cards. The earliest we can expect to see PCIe 6.0 devices in the PC market would be 2023 or 2024 depending on requirements.

Over the past few days, we've heard chatter about a new 12-pin PCIe power connector for graphics cards being introduced, particularly from Chinese language publication FCPowerUp, including a picture of the connector itself. Igor's Lab also did an in-depth technical breakdown of the connector. TechPowerUp has some new information on this from a well placed industry source. The connector is real, and will be introduced with NVIDIA's next-generation "Ampere" graphics cards. The connector appears to be NVIDIA's brain-child, and not that of any other IP- or trading group, such as the PCI-SIG, Molex or Intel. The connector was designed in response to two market realities - that high-end graphics cards inevitably need two power connectors; and it would be neater for consumers to have a single cable than having to wrestle with two; and that lower-end (<225 W) graphics cards can make do with one 8-pin or 6-pin connector.

The new NVIDIA 12-pin connector has six 12 V and six ground pins. Its designers specify higher quality contacts both on the male and female ends, which can handle higher current than the pins on 8-pin/6-pin PCIe power connectors. Depending on the PSU vendor, the 12-pin connector can even split in the middle into two 6-pin, and could be marketed as "6+6 pin." The point of contact between the two 6-pin halves are kept leveled so they align seamlessly.

The PCI-Express gen 6.0 specification reached an important development milestone, with the publication of its version 0.5 first-draft. This provides important pointers to PCI-SIG members on what features and design changes gen 6.0 hopes to bring, and what its all important number is - bandwidth. PCIe gen 6.0 quadruples per-lane bandwidth over gen 4.0 to 64 GT/s (double that of gen 5.0), resulting in bi-directional bandwidth of 256 GB/s in an x16 configuration.

The spec also introduces a new physical layer change, with PAM4 (pulse amplitude modulation) signaling replacing NRZ (non-return to zero), a key ingredient in the generational bandwidth doubling effort. Despite this, PCIe gen 6.0 retains backwards-compatibility with all older generations of PCIe, which could mean the PCIe slot on motherboards may not look any different. PCIe gen 6.0 also introduces FEC (forward error-correction), and has similar per-channel reach as PCIe gen 5.0. Our older article on Intel's proprietary CXL outlines a key feature of PCIe gen 5.0 besides its bandwidth doubling over gen 4.0 - scalability. Although targeting completion in 2021, it could take several more years for the technology to transcend enterprise computing segments and reach the client. PCI-SIG anticipates the need for gen 6.0 kind of bandwidth in the industry by 2025.

The PCI Express 4.0 specification was designed to double the performance of server and storage systems, pushing speeds up to 16.0 gigatransfers per second (GT/s) or 2 gigabits per second (Gb/s) throughput per lane, and driving new performance levels for cloud and enterprise applications. Today, KIOXIA America, Inc. (formerly Toshiba Memory America, Inc.) announced that its lineup of CM6 and CD6 Series PCIe 4.0 NVM Express (NVMe ) enterprise and data center solid state drives (SSDs) are now shipping to customers.

An established leader in developing PCIe and NVMe SSDs, KIOXIA delivers never-before-seen performance. KIOXIA was the first company to publicly demonstrate PCIe 4.0 SSDs and is now the first to ship these next-generation drives. The CM6 and CD6 Series SSDs are compliant to the latest NVMe specification, and include key features such as in-band NVMe-MI, persistent event log, namespace granularity, and shared stream writes. Additionally, both drives are SFF-TA-1001 conformant (also known as U.3), which allows them to be used in tri-mode enabled backplanes, which can accept SAS, SATA or NVMe SSDs.

KIOXIA America, Inc. (formerly Toshiba Memory America, Inc.), the U.S.-based subsidiary of KIOXIA Corporation, today announced that its lineup of PCIe 4.0 NVMeTM enterprise solid state drives (SSDs) has achieved PCI-SIG compliance for PCIe 4.0 and University of New Hampshire InterOperability Laboratory (UNH-IOL) certification. KIOXIA's CM6 Series successfully passed interoperability tests at the August 2019 PCI-SIG Compliance Workshop - the first workshop to include official PCIe 4.0 specification tests. KIOXIA America will be on hand at Supercomputing 2019 later this month to showcase new levels of flash performance enabled by its CM6 Series SSDs.

The first company to publicly demonstrate PCIe 4.0 SSDs, KIOXIA has established itself as a leader in developing PCIe 4.0 NVM Express SSDs and continues to push the limits of flash storage performance. The CM6 Series brings planned performance improvements of 3x over its PCIe 3.0 predecessors and is 12x faster than SATA drives. KIOXIA's lineup of Gen4 PCIe SSDs also includes the CD6 Series, which is targeted to cloud and scale-out environments.

With 64 Gbps bandwidth per lane, 256 Gbps in x4, and a whopping 1 Tbps in x16 (128 GB/s per direction), PCI-Express 6.0 will debut in 2021 as 5G adoption hits critical mass in markets across the globe, to support server nodes, high-bandwidth network infrastructure, and lighting fast I/O for HPC and AI applications. Development of the new standard is already underway, with the specification having achieved a pre-release version 0.3, according to the PCI-SIG, the body that develops and maintains the PCI IP.

Further development, prototyping, and testing of the standard will run through 2020 as drafts of the standard are dispatched to interested parties. With the specification published in 2021, the first devices implementing it could arrive the following year. Granted, very few devices need 1 Tbps bandwidth, but the exercise of doubling bandwidth every 3 or so years has its maximum impact on devices that only have wiring for one PCIe lane, and directly impacts bandwidth of other I/O specifications that are derived from PCIe, such as USB, Thunderbolt, CXL, etc.

Toshiba Memory America, Inc. (TMA), the U.S.-based subsidiary of Toshiba Memory Corporation, participated in the PCI-SIG (Peripheral Component Interconnect Special Interest Group) Compliance Workshop #109 in Burlingame, California, where several prototype and engineering samples of the company's upcoming PCIe 4.0 NVMe SSDs underwent PCI-SIG FYI Gen 4 testing.

The fourth generation of the PCIe interface, PCIe 4.0, doubles available bandwidth for graphics cards, SSDs, Wi-Fi, and Ethernet cards. The new standard will enable SSDs in particular to provide much higher performance than previous PCIe 3.0 SSDs, especially sequential read performance. An early participant seeking to enable PCIe 4.0 technologies, Toshiba Memory leverages its technology leadership role and actively collaborates with PCI-SIG and other member companies to accelerate adoption of the new interface standard.

"We realized years ago that the future of flash storage would be built on the NVMe architecture," noted John Geldman, director, SSD Industry Standards for Toshiba Memory America, Inc. and a member of the NVM Express Board of Directors. "This new and faster PCIe standard will maximize performance capability - unlocking systems' full potential."

This shouldn't really need to be spelled out, but AMD clarified that you can't have PCI-Express gen 4.0 running an upcoming Ryzen 3000 "Matisse" processor on older socket AM4 motherboards based on AMD 300-series and 400-series chipsets, and that the processor's PCIe root-complex will run at PCI-Express gen 3.0 speeds. AMD's official reason for this is that the older motherboards can't guarantee reliable signaling needed for PCI-Express gen 4.0 and hence the company decided to blanket-disable PCIe gen 4.0 for the older platforms. This statement was put out by Robert Hallock, senior technical marketing head for CPUs and APUs, on Reddit.

Unofficially, though, we believe there are technological barriers standing in the way of PCI-Express gen 4.0 on the older motherboards, the least of which are the lack of external PCIe gen 4.0-certified re-driver/equalizer components, and lane-switching on boards that split one x16 PEG link to two x8 links. There may be other less technical issues such as PCI-SIG certification for the older platforms. Intel faced a similar challenge with its 3rd generation Core "Ivy Bridge" processors, which introduced PCI-Express gen 3.0 to the mainstream desktop platform, and were backwards-compatible with Intel 6-series chipset (eg: Z68 Express). The older 6-series motherboards could only put out PCIe gen 2.0 with the newer processors.

PCI-SIG today announced the release of PCI Express (PCIe ) 5.0 specification, reaching 32 GT/s transfer rates, while maintaining low power and backwards compatibility with previous technology generations. "New data-intensive applications are driving demand for unprecedented levels of performance," said Al Yanes, PCI-SIG Chairman and President. "Completing the PCIe 5.0 specification in 18 months is a major achievement, and it is due to the commitment of our members who worked diligently to evolve PCIe technology to meet the performance needs of the industry. The PCIe architecture will continue to stand as the de facto standard for high performance I/O for the foreseeable future."

"For 27 years, the PCI-SIG has continually delivered new versions of I/O standards that enable designers to accommodate the never-ending increases in bandwidth required for next generation systems, while preserving investments in prior generation interfaces and software," noted Nathan Brookwood, research fellow at Insight 64. "Over that period, peak bandwidth has increased from 133 MB/second (for the first 32-bit parallel version) to 32 GB/second (for the V4.0 by16 serial version), a 240X improvement. Wow! The new PCIe 5.0 standard doubles that again to 64 GB/second. Wow2. We have come to take this increased performance for granted, but in reality, it takes a coordinated effort across many members of the PCI-SIG to execute these transitions so seamlessly."

CXL, short for Compute Express Link, is an ambitious new interconnect technology for removable high-bandwidth devices, such as GPU-based compute accelerators, in a data-center environment. It is designed to overcome many of the technical limitations of PCI-Express, the least of which is bandwidth. Intel sensed that its upcoming family of scalable compute accelerators under the Xe band need a specialized interconnect, which Intel wants to push as the next industry standard. The development of CXL is also triggered by compute accelerator majors NVIDIA and AMD already having similar interconnects of their own, NVLink and InfinityFabric, respectively. At a dedicated event dubbed "Interconnect Day 2019," Intel put out a technical presentation that spelled out the nuts and bolts of CXL.

Intel began by describing why the industry needs CXL, and why PCI-Express (PCIe) doesn't suit its use-case. For a client-segment device, PCIe is perfect, since client-segment machines don't have too many devices, too large memory, and the applications don't have a very large memory footprint or scale across multiple machines. PCIe fails big in the data-center, when dealing with multiple bandwidth-hungry devices and vast shared memory pools. Its biggest shortcoming is isolated memory pools for each device, and inefficient access mechanisms. Resource-sharing is almost impossible. Sharing operands and data between multiple devices, such as two GPU accelerators working on a problem, is very inefficient. And lastly, there's latency, lots of it. Latency is the biggest enemy of shared memory pools that span across multiple physical machines. CXL is designed to overcome many of these problems without discarding the best part about PCIe - the simplicity and adaptability of its physical layer.

AMD's socket AM4 and socket TR4 chipsets are originally designed by ASMedia. With its "Zen" family of processors being full-fledged SoCs, the motherboard "chipset" only serves to increase connectivity, and ASMedia already holds certifications for key groups such as the PCI-SIG, USB-IF, SATA-IO, NVM-Express group, etc. It's being reported now that ASMedia will develop some, if not all 500-series chipsets, with the exception of X570. The X570 will be an in-house design by AMD, which will use its own foundry partners (likely GloFo 14 nm) to manufacture it. This presents AMD with an opportunity to harden it against vulnerabilities, and have greater control over pricing, not to mention overcoming key design shortfalls of "Promontory," such as downstream PCIe connectivity.

This flies in the face of speculation that AMD would discontinue ASMedia's supply of chipset, especially in the wake of the "Chimera" vulnerability affecting "Promontory" 300-series and 400-series chipsets. The supposedly security-hardened 500-series chipset will feature PCI-Express gen 4.0 certification. What this means is that the chipset bus between the AM4/TR4 SoC and the chipset will be PCI-Express 4.0 x4 (64 Gbps), translating to double the bandwidth. It remains to be seen if the downstream PCIe lanes put out by the chipset are gen 4.0, too. Current 400-series chipsets continue to put out stale gen 2.0 lanes, compensated for by additional gen 3.0 lanes put out by the SoC. Sources also mention that ASMedia-supplied chipsets will only hit the market toward the end of 2019, which means AMD X570 could be the only 500-series chipset option between the mid-2019 launch of 3rd generation Ryzen, and late-2019. You should be able to run these processors on older socket AM4 motherboards via BIOS updates, though.

The SD Association announced today SD Express which adds the popular PCI Express and NVMe interfaces to the legacy SD interface. The PCIe interface delivering a 985 megabytes per second (MB/s) maximum data transfer rate and the NVMe upper layer protocol enables advanced memory access mechanism, enabling a new world of opportunities for the popular SD memory card. In addition, the maximum storage capacity in SD memory cards grows from 2 TB with SDXC to 128 TB with the new SD Ultra Capacity (SDUC) card. These innovations maintain the SDA's commitment to backward compatibility and are part of the new SD 7.0 specification.

"SD Express' use of popular PCIe and NVMe interfaces to deliver faster transfer speeds is a savvy choice since both protocols are widely used in the industry today and creates a compelling choice for devices of all types," said Mats Larsson, Senior Market Analyst at Futuresource. "The SD Association has a robust ecosystem with a strong history of integrating SD innovations and has earned the trust of consumers around the world."

AMD's second-generation Ryzen processors, which debut some time in Q1-2018, will be accompanied by the company's new 400-series motherboard chipset, even though they are expected to work with existing socket AM4 motherboards based on 300-series chipsets (with BIOS updates). The 400-series Promontory chipset surfaced on the PCIe Integrators List of PCI-SIG, the standards governing body of the PCI bus (which also oversees PCIe specifications development).

The listing seems to confirm that 400-series chipset will feature PCI-Express gen 3.0 general purpose lanes. These are downstream PCIe lanes put out by the chipset, to run the various external onboard controllers on the motherboard, and usually wired to the x1 and x4 PCIe slots. The current 300-series chipset only features up to 8 PCIe gen 2.0 general purpose lanes, and that was seen as a drawback. AMD Ryzen socket AM4 processors put out additional gen 3.0 lanes besides the 16 lanes allocated to PEG (one x16 or two x8, physically x16 slots); and 4 lanes serving as chipset bus. These additional gen 3.0 lanes typically drive a 32 Gb/s M.2 slot. With 400-series chipset bringing gen 3.0 general purpose lanes, one can expect newer socket AM4 motherboards with more than one 32 Gb/s M.2 slot (one from the SoC, another from the chipset).