Synopsys, Inc. today announced the industry's first complete IP solution for the PCI Express (PCIe ) 6.0 technology that includes controller, PHY and verification IP, enabling early development of PCIe 6.0 system-on-chip (SoC) designs. Built on Synopsys' widely deployed and silicon-proven DesignWare IP for PCIe 5.0, the new DesignWare IP for PCIe 6.0 supports the latest features in the standard specification including, 64 GT/s PAM-4 signaling, FLIT mode and L0p power state. Synopsys' complete IP solution addresses evolving latency, bandwidth and power-efficiency requirements of high-performance computing, AI and storage SoCs.

To achieve the lowest latency with maximum throughput for all transfer sizes, the DesignWare Controller for PCI Express 6.0 utilizes a MultiStream architecture, delivering up to 2X the performance of a single-stream design. The Controller, with available 1024-bit architecture, allows designers to achieve 64 GT/s x16 bandwidth while closing timing at 1 GHz. In addition, the controller provides optimal flow with multiple data sources and in multi-virtual channel implementations. To facilitate accelerated testbench development with built-in verification plan, sequences and functional coverage, the VC Verification IP for PCIe uses native SystemVerilog/UVM architecture that can be integrated, configured and customized with minimal effort.

GLOBALFOUNDRIES (GF ) today announced the release and distribution of OpenAccess iPDK libraries optimized for its 22FDX (22nm FD-SOI) platform. With its best-in-class performance, power consumption, and broad feature integration capability, GF's differentiated 22FDX platform is the solution of choice for designers and innovators working in 5G mmWave, edge AI, Internet of Things (IoT), automotive, satellite communications, security, and other applications.

The open-standard based iPDK offers the same level of functionality and performance as PDKs designed for specific vendor tools, while helping enable interoperability and compatibility among different design tool suites. Tools including: the Custom Compiler solution from Synopsys; TannerTM software solutions from Mentor, a Siemens business; PathWave Advanced Design System (ADS) from Keysight Technologies; and any other tool supporting OpenAccess will now be able to use GF iPDK libraries for its 22FDX platform. GF's iPDK will consist of OpenAccess technology files, symbols, component description format (CDF), TCL callbacks, netlisting information, and PyCells.

The 22FDX iPDK is released and available alongside other EDA-specific 22FDX PDK bundles.

Micron Technology, Inc., today announced a comprehensive enablement program which will provide early access to technical resources, products and ecosystem partners. The Technology Enablement Program will aid in the design, development and qualification of next-generation computing platforms that use DDR5, the most technologically advanced DRAM available.

Today's news builds on Micron's January announcement of DDR5 RDIMM samples and brings the industry one step closer to unlocking the value in next-generation, data-centric applications. Companies joining Micron in the DDR5 Technology Enablement Program include Cadence, Montage, Rambus, Renesas and Synopsys.

Today Starblaze announced the availability of the STAR1000P NVMe solid state drive (SSD) controller for high-end client and entry-level enterprise applications. Performance optimizations enable the new controller to achieve sequential reads at 3.6GB/second and sequential writes at 3.2GB/second, up to 50% higher than Starblaze's previous generation controller, STAR1000. The STAR1000P achieves random reads at 750K input/output operations per second (IOPS) and random writes at 600K IOPS, up to 120% higher than Starblaze's STAR1000. The STAR1000P features PCIe Gen3x4, NVMe 1.3 and eight flash channels to support up to 32 terabytes (TB) of storage. The STAR1000P also incorporates a multicore implementation of Synopsys' DesignWare ARC HS38 processor, taking advantage of ARC's extensible architecture with custom instructions that improve scheduling efficiency.

"Enterprise SSD applications need increasing processor performance to support much higher throughput with reduced latency," said John Koeter, vice president of marketing for IP at Synopsys. "Synopsys' ARC HS processors deliver the scalability that Starblaze needs to extend the performance of their STAR1000P platform for the rapidly evolving SSD controller market."

GLOBALFOUNDRIES today announced the establishment of Avera Semiconductor LLC, a wholly owned subsidiary dedicated to providing custom silicon solutions for a broad range of applications. Avera Semi will leverage deep ties with GF to deliver ASIC offerings on 14/12nm and more mature technologies while providing clients new capabilities and access to alternate foundry processes at 7nm and beyond.

Avera Semi is built upon an unrivaled legacy of ASIC expertise, tapping into a world-class team that has executed more than 2,000 complex designs in its 25-year history. With more than 850 employees, annual revenues in excess of $500 million, and over $3 billion in 14nm designs in execution, Avera Semi is well positioned to serve clients developing products across a wide range of markets, including wired and wireless networking, data centers and storage, artificial intelligence and machine learning, and aerospace and defense.

Synopsys has successfully carried out the world's first USB 3.2 demonstration. The host system was running on a Windows 10 operating system with the standard USB drivers without any modifications whatsoever. The USB 3.2 host controller was implemented on a HAPS-80 FPGA platform connected to the PHY board through a Type-C connector. The target system, which ran on Linux, used an identical hardware setup as the host system with the exception that it was configured as a Mass Storage device. The PHY employed in the demonstration was manufactured on the FinFET process and capable of operating at speeds up to 10 Gbps per lane. Therefore, Synopsys's solution consisted of pairing both lanes to achieve a combined throughput of 20 Gbps. The company also emphasized the fact that USB 3.2 doesn't require the use of special cables. For the demonstration, they utilized a pair of conventional Belkin USB 3.1 Type-C cables that you can find at your local Target store.

Micron Technology, Inc., today announced XTRMFlash memory, a faster NOR flash solution designed to revolutionize the way the electronics industry develops systems to meet the demand for "instant-on" performance and fast system responsiveness in automotive, industrial and consumer applications. Utilizing its new, low pin count interface that uses as little as 11 active signals, Micron's XTRMFlash memory outperforms other industry NOR Flash while also significantly reducing pin counts by as much as 75 percent from those found in Parallel NOR flash available in the market today. XTRMFlash memory provides system designers the ideal and fastest possible direct code execution NOR flash memory solution available to enable high-performance, yet small form-factor designs.

"Micron is committed to continued innovation in NOR flash memory," said Richard De Caro, director of NOR Flash for Micron's Embedded Business Unit. "We worked closely with our ecosystem partners and customers to understand their next-generation requirements for high-performance memory, and we have developed XTRMFlash memory as a result. XTRMFlash memory and the XTRMFlash interface have the potential to dramatically change the paradigm of the existing memory landscape by enabling a new category of high-performance and low pin count memory devices that can also extend beyond NOR Flash."

Synopsys, Inc., a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that it has collaborated with TSMC to provide support for voltage-dependent design rules in TSMC's 16-nm Custom Design Reference Flow. As part of TSMC's custom design infrastructure, TSMC has also certified Synopsys' Laker custom design solution and circuit simulation tools that deliver new capabilities for TSMC V0.5 16-nm FinFET process layout design rules, device models, and electromigration and IR-drop (EM/IR) analysis. TSMC and Synopsys will continue to collaborate on certification of the Synopsys tool set until 16 nm FinFET reaches V1.0.

"TSMC works with Synopsys to ensure our customers have access to analog and mixed-signal design tools for TSMC's 16-nanometer FinFET process," said Suk Lee, senior director of design infrastructure marketing at TSMC. "The Custom Design Reference Flow is another milestone of the long term collaboration between the two companies."

Synopsys, Inc., a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced TSMC's certification of Synopsys' Laker custom design solution for the TSMC 16-nanometer (nm) FinFET process Design Rule Manual (DRM) V0.5 as well as the availability of a 16-nm interoperable process design kit (iPDK) from TSMC.

With its robust support for the iPDK standard, Synopsys' Laker custom design solution provides users with access to a wide range of TSMC process technologies, from 180-nm to 16-nm. Along with support for the TSMC 16-nm V0.5 iPDK, the Laker tool has been enhanced to enable full use of FinFET technology.

Synopsys, Inc., a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the delivery of lithography compliance checking technology for the TSMC 20-nanometer (nm) DFM Data Kit (DDK) encapsulated with Synopsys Proteus mask synthesis technologies. As a result of the design-for-manufacturing collaboration between TSMC and Synopsys, the compliance checking engine in the DDK helps designers identify lithography-related problems early in the design development phase, avoid litho-related manufacturing issues and late-stage schedule slips resulting from re-design.

The TSMC 20-nm DDK complements traditional physical verification rules with a highly accurate simulation-based solution to identify design non-compliance using a direct simulation of the manufacturing process. Lithography correction and verification tools used in the manufacturing mask synthesis flow are embedded in the DDK, resulting in accurate hotspot detection to avoid litho-related manufacturing issues.

Synopsys, Inc., a global leader accelerating innovation in the design, verification and manufacture of chips and systems, today announced 20-nanometer (nm) process technology support for the TSMC 20 nm Reference flow. This includes Synopsys Galaxy Implementation Platform support for the latest TSMC 20 nm design rules and models. The collaboration between TSMC and Synopsys on 20nm technology allows designers to gain performance, power efficiency and chip density advantages while achieving predictable design closure with the industry-proven Synopsys RTL to GDSII solution.

TSMC's 20 nm Reference Flow addresses 20 nm design challenges with a transparent double patterning aware design flow enabling double patterning technology (DPT) compliance, pre-coloring capability, new RC extraction methodology, DPT sign-off, and integrated design-for-manufacturing (DFM). The new Reference Flow's transparent DPT enablement reduces DPT design complexity, achieves required accuracy, minimizes 20 nm design flow setup and learning curve, and accelerates 20 nm process adoption.

Synopsys, Inc., a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced a multi-year agreement to provide Advanced Micro Devices, Inc. (AMD) with its next-generation Discovery Verification IP (VIP). Based on the new VIPER architecture, the recently announced Discovery VIP family provides inherent performance, ease-of-use and extensibility to speed and simplify verification of the most complex system-on-chip (SoC) designs. This agreement covers a variety of VIP titles including USB 3.0, ARM AMBA AXI interconnect, SATA 3.0, PCI Express Gen 3, and MIPI, as well as Synopsys' Protocol Analyzer, a unique protocol-aware SoC debug environment.

"In our verification environment for Southbridge SoCs and IP cores, we utilize several interfaces, including AXI3 and USB 3.0. After an extensive evaluation, we selected Synopsys' next-generation Discovery VIP for several of our leading SoC designs," said Thomas Bodmer, manager of design engineering at AMD. "With Discovery VIP, we have seen benefits in minimizing our simulation runs and achieving higher coverage. We have used Synopsys' Protocol Analyzer technology to narrow down protocol violations and debug the root causes."