Intel is revisiting the concept of asymmetric multi-GPU introduced with DirectX 12. The company posted an elaborate technical slide-deck it originally planned to present to game developers at the now-cancelled GDC 2020. The technology shows promise because the company isn't insulting developers' intelligence by proposing that the iGPU lying dormant be made to shoulder the game's entire rendering pipeline for a single-digit percentage performance boost. Rather, it has come up with innovating augments to the rendering path such that only certain lightweight compute aspects of the game's rendering be passed on to the iGPU's execution units, so it has a more meaningful contribution to overall performance. To that effect, Intel is on the path of coming up with SDK that can be integrated with existing game engines.

Microsoft DirectX 12 introduced the holy grail of multi-GPU technology, under its Explicit Multi-Adapter specification. This allows game engines to send rendering traffic to any combinations or makes of GPUs that support the API, to achieve a performance uplift over single GPU. This was met with lukewarm reception from AMD and NVIDIA, and far too few DirectX 12 games actually support it. Intel proposes a specialization of explicit multi-adapter approach, in which the iGPU's execution units are made to process various low-bandwidth elements both during the rendering and post-processing stages, such as Occlusion Culling, AI, game physics, etc. Intel's method leverages cross-adapter shared resources sitting in system memory (main memory), and D3D12 asynchronous compute, which creates separate processing queues for rendering and compute.

Intel's upcoming Rocket Lake-S desktop platform is expected to arrive sometime later this year, however, we didn't have any concrete details on what will it bring. Thanks to the exclusive information obtained by VideoCardz'es sources at Intel, there are some more details regarding the RKL-S platform. To start, the RKL-S platform is based on a 500-series chipset. This is an iteration of the upcoming 400-series chipset, and it features many platform improvements. The 500-series chipset based motherboards will supposedly have an LGA 1200 socket, which is an improvement in pin count compared to LGA 1151 socket found on 300 series chipset.

The main improvement is the CPU core itself, which is supposedly a 14 nm adaptation of Tiger Lake-U based on Willow Cove core. This design is representing a backport of IP to an older manufacturing node, which results in bigger die space due to larger node used. When it comes to the platform improvements, it will support the long-awaited PCIe 4.0 connection already present on competing platforms from AMD. It will enable much faster SSD speeds as there are already PCIe 4.0 NVMe devices that run at 7 GB/s speeds. With RKL-S, there will be 20 PCIe 4.0 lanes present, where four would go to the NVMe SSD and 16 would go to the PCIe slots from GPUs. Another interesting feature of the RKL-S is the addition of Xe graphics found on the CPU die, meant as iGPU. Supposedly based on Gen12 graphics, it will bring support for HDMI 2.0b and DisplayPort 1.4a connectors.

Intel is rumored to be aligning its future-generation Xe GPU development with TSMC's node development cycle, with the company reportedly negotiating with the Taiwanese foundry for 6 nm and 3 nm allocation for its large Xe GPUs. Intel's first Xe discrete GPUs for the market, however, are reportedly built on the company's own 10 nm+ silicon fabrication process.

While Intel's fascination with TSMC 3 nm is understandable, seeking out TSMC's 6 nm node raises eyebrows. Internally referred to as "N6," the 6 nm silicon fabrication node at TSMC is expected to go live either towards the end of 2020 or early 2021, which is when Intel's 10 nm+ node is expected to pick up volume production, beginning with the company's "Tiger Lake" processors. Perhaps a decision has been made internally to ensure that Xe doesn't eat too much into Intel's own foundry capacities meant for processor manufacturing, and to instead outsource Xe manufacturing to third-party foundries like TSMC and Samsung eventually. Way back in April 2019 it was rumored that Intel was evaluating Samsung as a foundry partner for Xe.

Intel NUC 11 Extreme is the spiritual successor to the "Hades Canyon" and "Skull Canyon" NUC, and implements the company's next-generation 10 nm+ "Tiger Lake" processor. Codenamed "Panther Canyon," the NUC 11 Extreme represents a line of ultra-compact desktops with serious computing power, bringing together the company's highest-performance CPU cores and iGPUs. The "Tiger Lake-U" SoC powering the NUC 11 Extreme will reportedly be configured with a 28-Watt TDP, and will come in Core i3, Core i5, and Core i7 variants.

The "Tiger Lake-U" processor is expected to combine next-generation "Willow Cove" CPU cores with an iGPU based on Intel's new Xe graphics architecture, in what could be the first commercial outing for both. The NUC 11 Extreme "Panther Canyon" will also support up to 64 GB of dual-channel DDR4-3200 memory over SO-DIMMs, an M.2-2280 slot with PCI-Express 4.0 x4 and SATA 6 Gbps wiring, and option for Intel Optane M10 cache memory. On the connectivity front, and Intel AX-201 WLAN card provides 802.11ax Wi-Fi 6, and Bluetooth 5. A 2.5 GbE wired interface will also be available. These will also be among the first NUCs to feature front- and rear-Thunderbolt ports (possibly next-gen 80 Gbps given that the platform implements PCIe gen 4.0). The NUC 11 Extreme "Panther Canyon" is expected to launch some time in the second half of 2020.

At a media event on Wednesday, Intel invited us to check out their first working modern discrete graphics card, the Xe DG1 Software Development Vehicle (developer-edition). Leading the event was our host Ari Rauch, Intel Vice President and General Manager for Graphics Technology Engineering and dGPU Business. Much like gruff developer-editions of game consoles released to developers several quarters ahead of market launch, the DG1-SDV allows software developers to discover and learn the Xe graphics architecture, and develop optimization processes for their current and future software within their organizations. We walked into the event expecting to see a big ugly PCB with a bare fan-heatsink and a contraption that sort-of looks like a graphics card; but were pleasantly surprised with what we saw: a rather professional product design.

What we didn't get at the event, through, was a juicy technical breakdown of the Xe graphics architecture, and its various components that add up to the GPU. We still left pleasantly surprised for what we were shown: it works! The DG1-SDV is able to play games at 1080p, even if they are technically lightweight titles like "Warframe," and aren't maxing out settings. The SDV is a 15.2 cm-long graphics card that relies on the PCI-Express slot for power entirely (and hence pulling less than 75 W).

During this year's CES, Intel had an event called the Performance Workshop, where many things were presented. Among those are Intel's upcoming Comet Lake-H CPUs, Ghost Canyon NUC 9, and last but not the least there was a mention of the future Tiger Lake processor and its AI performance. Starting with the Comet Lake-H announcement, Intel promised to deliver 8 core, 16 thread processors that are capable of reaching as high as 5 GHz clock speeds, in a 45 W TDP. These processors are the answer to AMD's upcoming "Renoir" Ryzen 4000 series of mobile processors, which are rumored to feature up to 8 cores and 16 threads as well. The advertised 5 GHz boost on these Comet Lake-H CPUs is for the Core i7 model, while Core i9 SKUs are supposed to reach even higher speeds. All the system improvements tied to Comet Lake like support for WiFi 6, Thunderbolt 3 and Optane memory support are also present on these CPUs.

Today Intel's CPU based on yet unannounced architecture got revealed in the SiSoft benchmark database. Featuring six cores and twelve threads running at 3 GHz, it appears like a regular 14 nm CPU that's already available, however, when digging through the details, many things are revealed. The newly submitted CPU has a different L2 cache configuration from previous CPU offerings, with this chip featuring 1.25 MB of L2 cache per core, it is unlike anything else Intel currently offers. Ice Lake mobile chips feature 512 KB, while the highest amount of L2 cache is currently present on i9-10980XE, which features 1 MB of L2.

It is unknown where this CPU fits in the whole 14/10 nm lineup, as we don't know if this is an iteration of 10 nm Tiger Lake or the rumored 14 nm Rocket Lake CPU. All we know is that this CPU features new architecture compared to Skylake iterations that are currently being used, judging by L2 cache bump, which usually happens on new architectures. The platform used for benchmarking this CPU was SuperMicro X12DAi-N SMC X12 dual-socket motherboard, which featured two of these new CPUs for a total of 12 cores and 24 threads.

The "Willow Cove" CPU core design succeeds "Sunny Cove," Intel's first truly new CPU core design in close to 5 years. "Sunny Cove" is implemented in the 10 nm "Ice Lake" microarchitecture, and "Willow Cove" cores are expected to debut with the 10 nm+ "Tiger Lake." It turns out that Intel is working to adapt "Willow Cove" CPU cores onto a 14 nm microarchitecture, and "Rocket Lake" could be it.

Twitter user @chiakokhua, a retired VLSI engineer with high hit-rate on CPU microarchitecture news, made sense of technical documents to point out that "Rocket Lake" is essentially a 14 nm adaptation of "Tiger Lake," but with the iGPU shrunk significantly, to make room for the larger CPU cores. The Gen12 iGPU on "Rocket Lake-S" will feature just 32 execution units (EUs), whilst on "Tiger Lake," it has three times the muscle, with 96 EUs. "Rocket Lake" also replaces "Tiger Lake's" FIVR (fully-integrated voltage regulation) with a conventional SVID VRM architecture.

Intel's 11th generation Core "Rocket Lake-S" desktop processor will come in core-counts only up to 8, even as its predecessor, "Comet Lake-S," goes up to 10. Platform descriptors for Intel's next four microarchitectures surfaced on the web, detailing maximum values of their "S" (mainsteam desktop), "H" (mainstream notebook), "U" (ultrabook), and "Y" (low power portable) flavors. Both "Comet Lake-S" and "Rocket Lake-S" are 14 nm chips. "Comet Lake-S" comes with core counts of up to 10, a TDP of up to 125 Watts, Gen 9LP iGPU with 48 execution units, and native support for up to 128 GB of DDR4-2667.

The "Rocket Lake-S" silicon is interesting. Rumored to be yet another derivative of "Skylake," it features up to 8 CPU cores, the same 125 W maximum TDP, but swanky Gen12 iGPU with 32 execution units. The memory controller is also upgraded, which supports DDR4-2933 natively. There is no "Ice Lake-H" or "Ice Lake-S" in sight (no mainstream notebook or mainstream desktop implementations), ditto "Tiger Lake." For the foreseeable future, Intel will only make quad-core designs of the two 10 nm microarchitectures. "Rocket Lake-S" is slated for 2021 when, hopefully, we'll see Intel escape the 14 nm black hole.

With its "Skylake" microarchitecture, Intel significantly re-balanced the cache hierarchy of its HEDT and enterprise multi-core processors to equip CPU cores with larger amounts of faster L2 caches, and lesser amounts on slower shared L3 cache. The company retained its traditional cache balance for its mobile and desktop processor derivatives. This could change with the company's "Tiger Lake" microarchitecture, particularly the "Willow Cove" CPU cores they use, according to a Geekbench online database listing for a prototype quad-core "Tiger Lake-Y" mobile processor.

According to this listing, assuming Geekbench is reading the platform correctly; the "Tiger Lake-Y" processor features a 4-core/8-thread CPU, with a massive 1,280 KB (1.25 MB) of L2 cache per core, and 12 MB of L3 cache. Intel also enlarged the L1D (data) cache to be 48 KB in size, while the L1I (instruction) cache remains 32 KB. This amounts to a 400% increase in L2 cache size, and a 50% increase in L3 cache size. Unlike with "Skylake-X," the increase in L2 cache size doesn't come with a decrease in shared L3 cache size (per core). The "Tiger Lake-Y" processor is being tested on a "Corktown" prototyping platform (a specialized motherboard that has all possible I/O connectivity available with the platform, for testing. "Tiger Lake" is expected to make its debut some time in 2020-21 as a successor to "Ice Lake," and will be built on Intel's refined 10 nm++ silicon fabrication node. Find the Geekbench entry in the source link below.

Intel's Core "Tiger Lake" microarchitecture could be a point of transition between DDR4 and DDR5 for the company. Prototypes of devices based on the ultra-compact "Tiger Lake-Y" SoC were earlier shown featuring LPDDR4X memory, although a new device, possibly a prototyping platform, in the regulatory queue with the Eurasian Economic Commission describes itself as featuring a "Tiger Lake-U" chip meant for thin and light notebooks and convertibles. This device features newer LPDDR5 memory, according to its regulatory filing.

LPDDR5 succeeds LPDDR4X as the industry's next low-power memory standard, offering data-rates of up to 6,400 MT/s (versus up to 4,266 MT/s of LPDDR4X), and consumes up to 30 percent less power. This prototype at the EEC is sure to be using unreleased LPDDR5 memory chips as DRAM majors Samsung and SK Hynix plan to ship their DDR5-based memory solutions only by the end of this year, although mass-production of the chips have already started at Samsung, in PoP form-factors. A successor to the 10th generation Core "Ice Lake," "Tiger Lake" will be Intel's second CPU microarchitecture designed for its 10 nm silicon fabrication node.

In a shocking piece of news, Intel has reportedly scrapped plans to launch its 10 nm "Ice Lake" microarchitecture on the client desktop platform. The company will confine its 10 nm microarchitectures, "Ice Lake" and "Tiger Lake" to only the mobile platform, while the desktop platform will see derivatives of "Skylake" hold Intel's fort under the year 2022! Intel gambles that with HyperThreading enabled across the board and increased clock-speeds, it can restore competitiveness with AMD's 7 nm "Zen 2" Ryzen processors with its "Comet Lake" silicon that offers core-counts of up to 10.

"Comet Lake" will be succeeded in 2021 by the 14 nm "Rocket Lake" silicon, which somehow combines a Gen12 iGPU with "Skylake" derived CPU cores, and possibly increased core-counts and clock speeds over "Comet Lake." It's only 2022 that Intel will ship out a truly new microarchitecture on the desktop platform, with "Meteor Lake." This chip will be built on Intel's swanky 7 nm EUV silicon fabrication node, and possibly integrate CPU cores more advanced than even "Willow Cove," possibly "Golden Cove."

InstLatX64 has posted a CPU dump of Intel's next-generation 10 nm CPUs codenamed Tiger Lake. With the CPUID of 806C0, this Tiger Lake chip runs at 1000 MHz base and 3400 MHz boost clocks which is lower than the current Ice Lake models, but that is to be expected given that this might be just an engineering sample, meaning that production/consumer revision will have better frequency.

Perhaps one of the most interesting findings this dump shows is the new L3 cache configuration. Up until now Intel usually put 2 MB of L3 cache per each core, however with Tiger Lake, it seems like the plan is to boost the amount of available cache. Now we are going to get 50% more L3 cache resulting in 3 MB per core or 12 MB in total for this four-core chip. Improved cache capacity can result in additional latency because of additional distance data needs to travel to get in and out of cache, but Intel's engineers surely solved this problem. Additionally, full AVX512 support is present except avx512_bf which supports bfloat16 floating-point variation found in Cooper Lake Xeons.

Intel is slowly realizing plans to "one up" its GPU game starting from first 10 nm Ice Lake CPUs that feature Gen11 graphics, equipping users of integrated GPUs with much more performance than they previously got. Fortunately, Intel doesn't plan to stop there. Thanks to the recent pull request found on GitLab Mesa repository, we can now expect to receive biggest GPU performance bump in over a decade with the arrival of Gen12 based GPUs, found on next generation Tiger Lake processors.

In this merge request, Francisco Jerez, member of Intel's open source Linux graphics team, stated the following: "Gen12 is planned to include one of the most in-depth reworks of the Intel EU ISA since the original i965. The encoding of almost every instruction field, hardware opcode and register type needs to be updated in this merge request. But probably the most invasive change is the removal of the register scoreboard logic from the hardware, which means that the EU will no longer guarantee data coherency between register reads and writes, and will require the compiler to synchronize dependent instructions anytime there is a potential data hazard..."

Intel is working on its next generation gaming-grade NUC, codenamed "Phantom Canyon." When it comes out some time in 2020-21, it will feature Intel's 10 nm+ "Tiger Lake" SoC. Intel detailed this and more in a leaked presentation to industry partners. It describes the launch of of the company's "Ghost Canyon" NUC in Fall 2019 to succeed the current "Hades Canyon" gaming NUC. This box features a Core i9-9980HK processor and discrete graphics options. It will be succeeded in 2020-21 (late 2020 or sometime 2021), by the "Phantom Canyon" NUC that's in development.

The "Phantom Canyon" NUC is powered by a 28 W 10 nm+ "Tiger Lake-U" SoC that features PCI-Express gen 4. The package also implements Intel's "Gen 12" graphics processor that's derived from the Xe architecture it's currently working on, according to Chinese publication PTTWeb. The NUC will also feature discrete graphics options in the price-range of the current GTX 1660 Ti and RTX 2060 ($299 to $349). In related news, we see subtle hints that Intel will give its chipset bus a major update in future generations of its desktop and mobile platforms. Apparently, future platforms could feature DMI spread over 8 lanes as opposed to 4 on current platforms, besides the update to PCIe gen 4. This quadrupling in bandwidth compared to DMI 3.0 (PCIe 3.0 x4) is necessitated by the growth in bandwidth-hungry devices such as NVMe SSDs, external Thunderbolt 3 graphics cards, USB 3.2 flash drives, etc.

Even as Intel banks on 10 nm "Ice Lake" to pull it out of the 14 nm dark ages, the company is designing a fascinating new monolithic processor SoC die that succeeds it. Codenamed "Tiger Lake," and slated to debut in 2020, this die packs "Willow Cove" CPU cores and an iGPU based on Intel's Xe architecture, not Gen11. "Willow Cove" CPU cores are more advanced than the "Sunny Cove" cores "Ice Lake" packs, featuring a redesigned on-die cache, additional security features, and transistor optimization yielded from the newer 10 nm+ silicon fabrication process.

Intel is already boasting of 1 TFLOP/s compute power of the Gen11 iGPU on "Ice Lake," so it's logical to predict that the Xe based iGPU will be significantly faster. It will also support the latest display standards. The "next-gen I/O" referenced by Intel could be faster NVMe, Thunderbolt, and USB standards that leverage the bandwidth doubling brought about by PCI-Express gen 4.0. Here's the catch: much like "Ice Lake," the new "Tiger Lake" chip will get a mobile debut as Tiger Lake-Y or Tiger Lake-U, and desktop processors could follow later, possibly even 2021, depending on how much pressure it faces from AMD.

Intel revealed the very first hint at its post-"Ice Lake"/"Tiger Lake" processor lineup, which will likely be built on the company's 7 nanometer silicon fab process. Its 12th generation Core processor will be built on the new "Sapphire Rapids" silicon, which will be a major micro-architecture change, and could put 8-core into more hands. The processor, along with its companion chipset, will make up the "Tinsley" platform, which is expected to hit the market in 2020.

Following its 8th generation Core "Coffee Lake" lineup, Intel could built 2-3 micro-architectures on its new 10 nm process, namely "Cannon Lake," "Ice Lake," and "Tiger Lake," which could be released over the next three years. "Sapphire Rapids" could be launched on the process that succeeds 10 nm, likely 7 nm, with a launch timeline likely around 2020.

Intel's silicon fabrication has evidently hit a huge roadblock. It turns out that not just "Kaby Lake," but its two successors "Cannon Lake" and "Coffee Lake" could also be built on the 14 nm node, at best with a few process-level improvements. "Coffee Lake" is the company's 9th generation Core architecture, which is two steps ahead of even the "Kaby Lake" architecture, which is due later this year. "Kaby Lake" makes its way to the 45W mobile (H-segment) and 15W mobile (U-segment), in Q4-2016 and Q3-2016, respectively. The 15W U-segment will be augmented by "Cannon Lake" (8th generation Core) in Q4-2017. By mid-2018, Intel plans to launch "Coffee Lake" across both H- and U-segments.

According to a "Hot Hardware" report, based on a job listing for a systems engineer at the company, Intel could be staring at the scary prospect of holding out on 14 nm for the next three years, only to be relieved by the stopgap 10 nm node, which makes its debut with the 10th generation Core "Tiger Lake" architecture, due for 2019. "Tiger Lake," its succeeding "Ice Lake," and one other architecture could be launched on 10 nm, before finally deploying 7 nm around 2022.

With Intel's "tick-tock" product development cycle slowing down to a 3-launch cadence per silicon fab process, the company is preparing to launch no less than three micro-architectures on its next 10 nanometer silicon fab process. The first 10 nm CPU by Intel will launch in 2017.

In 2016, Intel will launch its 7th generation Core "Kaby Lake" processor, its third chip on the 14 nm process (after "Broadwell" and "Skylake"). The first 10 nm micro-architecture will be codenamed "Cannonlake," and will launch some time in 2017. Intel will build chips on the 10 nm for two more generations after "Cannonlake." The company's 2018 micro-architecture, built on the 10 nm will be codenamed "Icelake," and its 2019 release will be codenamed "Tigerlake." It's only 2020 that the company will pull out its next silicon fab process, 5 nm.