Synopsys, Inc., a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the delivery of lithography compliance checking technology for the TSMC 20-nanometer (nm) DFM Data Kit (DDK) encapsulated with Synopsys Proteus mask synthesis technologies. As a result of the design-for-manufacturing collaboration between TSMC and Synopsys, the compliance checking engine in the DDK helps designers identify lithography-related problems early in the design development phase, avoid litho-related manufacturing issues and late-stage schedule slips resulting from re-design.

The TSMC 20-nm DDK complements traditional physical verification rules with a highly accurate simulation-based solution to identify design non-compliance using a direct simulation of the manufacturing process. Lithography correction and verification tools used in the manufacturing mask synthesis flow are embedded in the DDK, resulting in accurate hotspot detection to avoid litho-related manufacturing issues.

"We share TSMC's commitment to the success of our mutual customers and look forward to continuing to provide the latest software technology supporting TSMC's most advanced processes and technology nodes," said Tom Ferry, senior marketing director of the Silicon Engineering Group at Synopsys. "Our close collaboration with TSMC to develop the 20-nanometer DDK helps bridge the gap between design and manufacturing, enabling TSMC to work efficiently with their customers to achieve faster volume ramps and more predictable product release cycles."

"The 20-nanometer DDK gives designers access to simulation-based hotspot detection, so they can efficiently identify out of compliance areas and take corrective action before manufacturing." said Suk Lee, senior director of Design Infrastructure Marketing at TSMC.