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AMD Opteron 4340

6
Cores
6
Threads
95 W
TDP
3.5 GHz
Frequency
3.8 GHz
Boost
Seoul
Codename
Socket C32
Socket
AMD Socket C32
AMD Socket C32
The AMD Opteron 4340 is a server/workstation processor with 6 cores, launched in December 2012. It is part of the Opteron lineup, using the Seoul architecture with Socket C32. To further increase overall system performance, up to two Opteron 4340 CPUs can link up in a multi-processor (SMP) configuration. Opteron 4340 has 8 MB of L3 cache and operates at 3.5 GHz by default, but can boost up to 3.8 GHz, depending on the workload. AMD is building the Opteron 4340 on a 32 nm production process using 1,200 million transistors. The multiplier is locked on Opteron 4340, which limits its overclocking capabilities.
With a TDP of 95 W, the Opteron 4340 consumes a good deal of power, so decent cooling is needed. AMD's processor supports DDR3 memory. This processor lacks integrated graphics, you might need a graphics card.
Hardware virtualization is available on the Opteron 4340, which greatly improves virtual machine performance. Programs using Advanced Vector Extensions (AVX) will run on this processor, boosting performance for calculation-heavy applications.

Physical

Socket: AMD Socket C32
Process Size: 32 nm
Transistors: 1,200 million
Die Size: 315 mm²
Package:

Processor

Market: Server/Workstation
Production Status: unknown
Release Date: Dec 4th, 2012
Part#: OS4340WLU6KHK

Performance

Frequency: 3.5 GHz
Turbo Clock: up to 3.8 GHz
Base Clock: 200 MHz
Multiplier: 17.5x
Multiplier Unlocked: No
TDP: 95 W

Architecture

Codename: Seoul
Generation: Opteron
(Seoul)
Memory Support: DDR3
ECC Memory: No

Core Config

# of Cores: 6
# of Threads: 6
SMP # CPUs: 2
Integrated Graphics: N/A

Cache

Cache L1: 288 KB
Cache L2: 6 MB
Cache L3: 8 MB (shared)

Features

  • MMX
  • SSE
  • SSE2
  • SSE3
  • SSSE3
  • SSE4.1
  • SSE4.2
  • SSE4a
  • AMD64
  • AMD-V
  • AES
  • AVX
  • CLMUL
  • CVT16
  • EVP
  • FMA4
  • FMA3
  • XOP

Notes

16KB L1 data cache per core.
64KB L1 instruction cache shared per two cores (per module).
2MB L2 cache shared per two cores (per module).
Nov 21st, 2024 07:48 EST change timezone

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