OK it took me a few days but here go's
If we take a look at a single Bulldozer core, you see a design optimized for throughput AMD will not introduce its own version of Hyper-Threading, but rather focus on physically increasing the number of instructions per clock [IPC] through wider internal units. A good example will be the newly designed 128-bit FPUs [Floating-Point Units]. Currently, 128-bit instructions are carried out by using 32-bit / 64-bit FPU at a reduced efficiency [more cycles needed to process a single instruction]. According to our sources, GPR [General Purpose Registers] were increased to 128-bit. Once that we learned of this alleged GPR depth, we asked does that mean we can, theoretically, call Bulldozer a "128-bit CPU" and is "x86-128" on the way? I will openly admit that I asked such a question without giving it a second thought.
Most people are using X86 64 bit processors, the bulldozer is really the first 128 bit X86 cpu.
I believe the focus of AMD's design was to increase the number of instructions processed on-the-fly, meaning that most instructions should use registers in a 64+64-bit or 32+32+32+32-bit fashion, significantly raising the IPC when compared to current K10.5 architecture. So, no "x86-128". For now.
This new internal architecture enabled AMD to design its first Streaming SIMD Extension set, 128-bit SSE5. Again, this was also the reason why Intel went into a denial frenzy over a possible implementation of the SSE5 instruction set. They cannot do it [SSE5] until they really change their architecture, "But we will blow them out of the water"… were the words from one of the e-mails I have with a friend and CPU designer from AMD when SSE5 development took place [thus, pre-AVX].
While it is currently true that 128-bit SSE instructions were executed slower due to reliance on 32 and 64-bit registers for FPUs, we have to wait and see who will have better a FPU unit: 512-bits Vector unit inside Larrabee or 128-bit Bulldozer ones.
One part that is bound to bring confusion is the memory controller. To be perfectly honest, both K10 [Phenom] and K10.5 [Phenom II] did a pretty lame job with asynchronous clock between the CPU cores and a "Northbridge" block consisting out of memory controller, I/O protocols and L3 cache. The fact that L3 cache worked at a lower clock significantly reduced its usability - you can get a higher performance boost if you overclock the "Northbridge", than raising CPU cores until they crash.
Bulldozer brings even more complexity into the frame - M-SPACE enables GPU-like clock gating, and processors based upon Bulldozer core should offer power efficiency one step ahead of most efficient notebook processors. The memory controller is continuing to be independently clocked, and L3 cache is now a default part of the architecture for both sides in CPU arena.
If we talk about the width, here comes the interesting part: AMD's memory controller can be 144-bit, 288-bit or even 576-bit [on MCM processors], but we doubt that we will ever see a 576-bit interface. MCM modules will feature a unison of two dies and a merger of cores and L3 cache from one unit with another, bypassing the external memory addressing - thus remaining 288-bit wide even with two physical 288-bit interfaces embedded in silicon.
With Virtualization or AMD-V continuing to be one of key architectural accents, the memory controller features a lot of technologies that will ease life to numerous virtual hosting providers. Every core can address a single channel or use one channel for redundancy, yet another feature from Alpha 21364 architecture.
Since AMD is pairing Bulldozer with the JEDEC-certified DDR3-1600 memory spec, you can expect to see memory bandwidth ranging from 25.6-51.2 GB/s. This part is heavily influenced with the underground overclocking department inside AMD. Those guys will expose a *lot* of advanced memory options exposed in the CPU design, so Orochi which is the desktop bulldozer should have no problems running DDR3-2000 or DDR3-2133 without overclocking the CPU itself.
I tried to break it down into English I hope this helps.
