Timing rules

[LAN_deRf_HA]

Working on tightening my timings, mainly secondary at this point, and I keep seeing people mentioning rules that many don't seem to follow. Like tRAS is supposed to stay above CL + tRCD + 2, but I've plenty of people drop tRAS to the floor without issue. I've seen a similar formula for tFAW.

And for stuff like tREF and tRFC what increments am I supposed to move those in? They're both such random numbers it makes me feel like they're supposed to follow a formula.

 

[d1nky]

ive been doing this also

what ive learnt, two days studying.... got a headache as well lol

http://forum-en.msi.com/faq/article/ddr3-memory-timings-explained


in my notes i got some formulas for better timings.

so far im 2500mhz 11-13-13-31 1T 300ns 1.65v fully stable


heres some for rock solid stable:

TRAS = CL + TRCD + TRP (+/-1)

TRC = TRAS + TRP

TWR = TCL-1 + burst length/2 + TWTR


some for tighter:

TRC = CL + TRAS

TRAS = TCL + TRCD + TRP/2 + 2


What im looking for is if there is a calculation to guage whether higherspeed/looser timing vs lowerspeed/tighter timing

its easy doing a maxmem/aida test but theyre inconsistent and are based on cpu/cpunb/ht which changes with frequencies

 

[LAN_deRf_HA]

TRAS = CL TRCD TRP ( /-1)

Not sure I buy this. Kits don't even follow this from the factory. You aren't, I'm not, nobody is. Just seems plain wrong. And this is what I keep running into which makes me think nobody knows what they're talking about.

Also why does quoting get rid of plus signs?

 

[d1nky]

its in that guide. i used there formulas on a lot of factory kits and most are out.

but if ya read that article it explains tras cant be completed until cl-trcd-trp has completed.

not many peple do know the timings thing, ive been learning for about a week and asked but didnt get many responses.

ive even learnt about block cycles and shit

however those formulas (stability) ones got me a memtest pass at 2600mhz

 

[LAN_deRf_HA]

I see nothing in that guide that explains why their tRAS formula doesn't match any kit I've seen. You say you followed it for 2600 but not for 2500? Cause 11+13+13=37, not 31.

 

[d1nky]

that got me bootable on something ive never booted on before.

the other formulas i posted (tighter) ones are what im using.

if that passes, i drop tras or trc down one until it errors, then voltage back down until it errors, and finally try 1T

 

[LAN_deRf_HA]

Just confuses me when there are rules you don't really need to follow. Are we hurting performance by running tRAS so low, and if so why are kits shipped with those timings in the first place?

its easy doing a maxmem/aida test but theyre inconsistent and are based on cpu/cpunb/ht which changes with frequencies

I do all those plus pi, but I repeat them and look at the averages, going by that I want to dig into tRFC next. Haven't even tried testing tREF, it's at 8320. Now what am I supposed to do with that? Not moving it one notch at a time that's for sure.

 

[d1nky]

i dont tbh, i was trying to work out why all profiles dont match the formulas. i guess its stability at said speed.

im subbed to this as i want to know more.

maybe some other more experienced people may know.. hopefully

 

[LAN_deRf_HA]

Trying to give the stable formulas a try but I can't find anything resembling burst length/2 on my Asus board.

Ok tried a few things. tREF hurt my performance. tRFC gave me the biggest latency drop I've seen on secondary timings. tRAS didn't seem to effect score with either the loose or tight formula, but loose let me boot a lower tRFC.

 

[d1nky]

burstlength for DDR3 = 8. its binned code or something. forgot to mention so BL/2 = 4

ive left the majority of subtimings alone. as the formulas didnt help, i used

TRC = CL + TRAS

TRAS = TCL + TRCD + TRP/2 + 2

and tightened them up again.

ive also been told that lower ns latency damages the ram at higher speeds. i.e 160ns and less.

i would love to know the formula RAM makers use.


today ill test some more, as i want to guage speed vs timing

 

[LAN_deRf_HA]

So far tFAW, tWCL, tREF, tRRD, and tRAS haven't helped my scores in any of the "short" benchmarks. Maybe a longer test would expose something, but it's not worth 10 hours of memtest if I'm not seeing the benefit.

I think my last tweak will be the tRFC as the drop in latency I got from cutting that in half was equal to a tRCD drop.

 

[The Von Matrices]

I remember reviews of the Athlon 64 with DDR1 memory being sensitive to TRAS. There was an optimal timing where memory bandwidth would peak and the reviewers would need to test each new processor model to see what the optimal TRAS was. They did tests like the one below http://www.anandtech.com/show/1948/5. I am not sure if this is still the situation with more modern processors and memory controllers.

 

[Velvet Wafer]

Changing the Refresh rate from 7.8 to 3.9 can be VERY important, dependant on the module... the 2400 Transcend 10-13-11 i have, require that, my Gskill 2000 9-9-9 do not, to reach good speeds and timings...tREF does matter too, but it was negligible compared to the first one...having a low TRC improves the Latency and throughput of the NB too, at least on AM3

 

[d1nky]

ive just been testing a few different configs.

i loaded 2133mhz with 1600 jedec subtimings, and well it knocked TEN minutes off a memtest pass. i thought wow! but the end was full of errors. so sub timings matter a lot.

that older stuff from reviews etc is a bit obsolete so ive heard.


here is a comparison between stock 2133 and 2500mhz(slightly looser)



i really need to work on the subtimings to squeeze more out but 1T gives me a gain again.


i feel like emailing Gskill asking for a formula!

 

[Aquinus]

You know, it's exceedingly difficult to find information on secondary timings, as I'm sure you're aware (I assumed you tried to Google it first). My understanding of DRAM timings in general is that many timings overlap with respect to when they actually occur during any memory operation and several timings occur within the primary timings. The real benefit from reducing secondary timings would really be to stabilize lower primary timings at any given frequency as opposed to actually improving performance. Beyond that, I'm not sure if I can be very helpful.

 

[d1nky]

many timings overlap with respect to when they actually occur during any memory operation and several timings occur within the primary timings

we need a formula for just that or some sort of rule.

its easy knocking numbers down but its difficult to find an order or the correct way. from what ive read there is a formula in the madness but no one knows, publicly anyway.

for example if, CL-TRCD-TRP-TRAS were x-x-x-x

what would the subtimings be....

and looking at my jedec profiles the subtimings follow some sort of formula as they are all different.



HELP IS NEEDED

 

[Aquinus]

we need a formula for just that or some sort of rule.

No you don't. You need to understand what you're changing, not use a forumula that figures it out for you. It's not that simple and it varies between any different DRAM ICs.

 

[d1nky]

to understand it all, well id basically need a PHD in dram.

ive been reading up on these two links for some time, and its still not clear

so excuse me if i seem like a noob, but i do need some direction

http://en.wikipedia.org/wiki/Dynamic_random-access_memory
http://forum-en.msi.com/faq/article/ddr3-memory-timings-explained


edit lost another link

 

[Aquinus]

to understand it all, well id basically need a PHD in dram.

Yeah, basically. What the descriptions of the timings do makes sense when you know what the DRAM is doing. I recommend learning a bit about DRAM or just leaving them be. You're not going to see any amazing benefits from changing secondary or tertiary timings, even if you know exactly what you're doing.

You're looking for an easy answer where these is none. I'm just saying.

 

[d1nky]

yea i do feel its all over my head, i actually got a headache the other day from reading for several hours.


i guess ill keep my secondary timings the same, oc higher speeds and try keep the main ones as tight as possible. currently stable @ 2500mhz 11-13-13-31 1T

my copy/read/write really depend on cpu speed but have gained, latency has dropped loads. and at stock cpu speeds ive gained a few fps in physics, just from oc ram.

maybe when im older ill get a phd in dram but im too young now lol

i can see why many people dont have a clue about subtimings

 

[Aquinus]

maybe when im older ill get a phd in dram but im too young now lol

A bachelors in computer science or electrical engineering will typically help. There isn't really isn't such a thing as a Ph.D in DRAM.

 

[d1nky]

NO wayy..... LOL

sorry lan derf ha for overtaking the thread.

 

[LAN_deRf_HA]

I'm a bit surprised it's not more well covered because you'd think anyone who is serious about benchmarking would be dealing with this regularly. I know I found at least one sub-timing that's reducing my latency by a whole point.

 

[d1nky]

would be nice if there were some sort of order/calculation without having to understand the ins and outs oof memory.

 

[LAN_deRf_HA]

It seems motherboard bios come with some basic ability in that regard with auto settings when you increase clock speed, but it's hit or miss.