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AMD Dragged to Court over Core Count on "Bulldozer"

qubit

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No you can set it to 1,2, or 4.
I can set it to 3, I double checked just before posting. Note that I've got a 2700K, so perhaps this restriction applies to later CPUs?

I can even set it to 3 cores + HT if I want to. Weird but true.

And when Ford rebutts something it stays rebutted. Especially when he has qubit backing him up.
I think I've just been Fricked. :wtf: :p
 
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I can set it to 3, I double checked just before posting. Note that I've got a 2700K, so perhaps this restriction applies to later CPUs?

I can even set it to 3 cores + HT if I want to. Weird but true.


I think I've just been Fricked. :wtf: :p

Are you referring to 3 active cores or limiting boost per core?
 

qubit

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Are you referring to 3 active cores or limiting boost per core?
3 active cores. Task Manager actually shows three graphs. Perhaps we're at cross purposes? lol. :)

Incidentally, when I first built my system, I of course posted about it on TPU. I then couldn't resist playing a little joke on everyone by saying how pleased I was with my new "5 core" CPU and actually posted a screenshot of TM running 5 threads. :laugh: The best bit was that it actually took a little while for people to catch on, lol.
 
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3 active cores. Task Manager actually shows three graphs. Perhaps we're at cross purposes? lol. :)

Incidentally, when I first built my system, I of course posted about it on TPU. I then couldn't resist playing a little joke on everyone by saying how pleased I was with my new "5 core" CPU and actually posted a screenshot of TM running 5 threads. :laugh: The best bit was that it actually took a little while for people to catch on, lol.

Well I swear the bios in my PC doesn't let me do it - and it is one of the highest end Z87 motherboards. Maybe they did just disable it in later archs.

Still though , I maintain my position that if they could, they would have made 3 core cpu's.
 
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This thread broke new world record? :eek:
 
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AMD is always up to shady business like this. They need to learn a big lesson and stop trying to cheat
 
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AMD is always up to shady business like this. They need to learn a big lesson and stop trying to cheat

And hyperthreading wasn't Intel's way of trying to trick their less technology aware consumers into thinking they have a genuine 8 core?

Anyways its up to the judge to determine if AMD is a cheat. Not us.
 
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And hyperthreading wasn't Intel's way of trying to trick their less technology aware consumers into thinking they have a genuine 8 core?

Anyways its up to the judge to determine if AMD is a cheat. Not us.
Intel never said it was 8 cores while amd did. BIG difference
 
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Intel never said it was 8 cores while amd did. BIG difference

Maybe Intel dont say 8 core on the box but its clear that most non enthusiasts think when they see 8 graphs in the task manager they assume it means 8 cores. Intel have done little in terms of trying to educate the non-enthusiasts consumer about how hyper threading works. Intel are happy for consumers to believe what they believe which is fine.

Anyways AMD might have a genuine 8 core, its all up to interpretation look at this thread alone you can make a good argument either way. None of us here can say definitively whether AMD is in breach of anything. Lets wait for the legal system to decide.
 
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Pretty sure he's going to win. I don't think there's any nomenclature to properly describe Bulldozer's design and even if it had existed, AMD wasn't using it.


x264 HD Benchmark runs on GPU and AMD undeniably has a stronger GPU in FX-8150 than Intel has in i7-2600K. The problem stems from floating point operations executed on the CPU. If you heavily load the FPUs in one core, the FPU performance of both cores will effectively half.


you can overload HT too.

amd will win this if the judge is clued up, if not.....
 
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no wonder he's a dick lol
 
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you can overload HT too.

amd will win this if the judge is clued up, if not.....

In big cases there will be a panel of impartial technology lawyers which will explain the technologies behind the architecture to the judge. I would think AMD would bring their own engineers as part of their defence too
 
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Wow.... 9 pages? Have the jury come to a decision yet?
 
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Verdict is amd screwed their costumers by lying for years
They screwed their financials for 5 years and brought the company very close to bankruptcy. They also screwed the hopes of AMD fans with processors that unfortunately are not competitive to Intel and with no money to support their platforms we haven't seen Steamroller FX chips, Excavator APUs, or Beema based AM1 chips. They didn't even had money to create a totally new GPU to take full advantage of HBM1. They could just implement HBM memory on two Tonga cores, that they glued together, and here it is, the new Fiji GPU, with only 32+32=64 ROPs losing from GM200 when it should be beating it.
But no, they didn't screw their customers because they always price their products based on the performance those products offer compared to Intel products. Anyone hoping to get a quad core FX chip and beat a 3-5 times more expensive i5, well, why pay for an FX chip? Go and buy a cheap quad core Braswell tablet/miniPC/Stick/whatever and destroy that i5 Skylake. Right? Riiiiiiiggghhhttttt.........
 

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AMD has, in a very real sense, been thoroughly punished for the CPU it brought to market in 2011 — and this lawsuit makes claims that don’t hold up to technical scrutiny.
http://www.extremetech.com/extreme/...lse-bulldozer-chip-marketing-is-without-merit

It's an argument which appears to rest wholly on the presence of only four FPU cores on the eight-core chip, but one which Dickey may struggle to win: floating-point units have not always been integral to processor designs, with early processors being integer-only models which emulated floating-point mathematics internally and the first FPUs themselves being entirely separate chips used as a co-processor, so to argue that the core-count of a chip is tied directly to the number of FPU units present is an interesting tactic - doubly so when it is entirely possible for the processor in question to run eight integer-based threads simultaneously.
http://www.bit-tech.net/news/hardware/2015/11/09/amd-bulldozer-core-count-suit/1

I'm apparently not the only person who thinks the FPU claim for what constitutes a core is bogus.
 

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Maybe Intel dont say 8 core on the box but its clear that most non enthusiasts think when they see 8 graphs in the task manager they assume it means 8 cores. Intel have done little in terms of trying to educate the non-enthusiasts consumer about how hyper threading works. Intel are happy for consumers to believe what they believe which is fine.
They always refer to # cores w/ HT or # cores w/o HT. Intel never claims SMT is equal to more cores like AMD does with Bulldozer.

you can overload HT too.
Not really. The underlying core will report 100% use. All threads are still simultaneously executed.

As previously discussed: You have to go back 25 years to find those dinosaurs in the x86 market. They're dead for a reason and Bulldozer suffered a similar fate.

The FPU uses SMT. I'd argue that any core that uses SMT excludes itself from equating threads to cores.
 
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They always refer to # cores w/ HT or # cores w/o HT. Intel never claims SMT is equal to more cores like AMD does with Bulldozer.


Not really. The underlying core will report 100% use. All threads are still simultaneously executed.
No they're scheduled, not executed. It states that in the whitepaper as I said earlier. 12 "core" Xenon can send 6 commands per clock. If it was 12 the scaling would be a lot closer to Piledriver.
The redeeming feature for Intel is AMD's slow cache.
 

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A lot of every processor in existence takes more than one clock to complete a task. While the FPU is crunching on something, SMT allows another thread to be processed through the ALU which takes far fewer clocks. Another example is a thread having to wait because of a cache miss, the other thread keeps executing. Like Bulldozer, after instructions are decoded, a lot of the processor is out-of-order and that is where SMT occurs. The only thing different about Bulldozer is that there are two ALUs instead of one. The rest of the processor mimics SMT. I would never call a core with two ALUs a dual core.
 
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Verdict is amd screwed their costumers by lying for years

So your a lawyer or a judge? Maybe you are a clairvoyant and can predict the outcome of the court case?

They always refer to # cores w/ HT or # cores w/o HT.


I agree Intel has done nothing wrong. Just saying Intel doesn't go out of their way to educate consumers what Hyperthreading is and 90% of their customers will assume its a core or functions the same as one. I'm not saying Intel should be obliged morally or legally to explain either just pointing out this fact.


Intel never claims SMT is equal to more cores like AMD does with Bulldozer.

To be fair it could be equal to, or equivalent to or classified as more cores until the verdict of the court case says otherwise. At the moment AMD has done nothing wrong. Its like a guilty until proven innocent witch hunt.
 
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A lot of every processor in existence takes more than one clock to complete a task.
Bullshit. There are a lot of instructions that not only execute in 1 second cycle, it can sometimes do several of the same instruction at once.

Before I grab part of this document, I will quote it:
LNN means latency for NN-bit operation. TNN means throughput for NN-bit operation. The term throughput is used to mean number of instructions per cycle of this type that can be sustained. That implies that more throughput is better, which is consistent with how most people understand the term. Intel use that same term in the exact opposite meaning in their manuals.
instructions-jpeg.jpg

Source: https://gmplib.org/~tege/x86-timing.pdf
Lets look at Sandy Bridge for a minute:
add, sub, and, or, xor inc, dec, neg, and not all execute in a single clock cycle and can process 3 of these uOps at once per core. Haswell expanded that to 4 uOps per cycle from 3 on SB. Even AMD's K10 was the same way but then you look at AMD's BD1 (which is what we're all huffy about,) and you notice that these same instructions can only do 2 uOps per clock cycle on Bulldozer. Then there are cases like double shift left and right which has a fraction of the performance on BD versus modern Intel CPUs.

People need to get their information right. Bulldozer is slow because dedicated components are skimped on, the fact that instructions usually take the same number of cycles as its Intel counterpart in many cases however, have much less throughput resulting in uOps having to be run more often than they would otherwise, which increases latency and translates certain full instructions into a longer set of uOps because of the CPU. So you might have an instruction with uOps that an Intel CPU could execute in one clock cycle but the AMD CPU might need two because it doesn't have enough resources in a single core to do it all at once.

For what its worth, Intel cores might not execute instructions "faster" but, it's that they can do more of them in a single clock cycle but both AMD and Intel both have a lot of core x86 instructions that not only occur in one cycle but, can execute multiple of the same uOps in the same cycle, which is where pipelining comes into play for instructions that allow pipelining.

It's also worth noting that there are x86 instructions that are not pipelined for various reasons. That's in this other document:
http://www.intel.com/content/www/us...-ia-32-architectures-optimization-manual.html
 
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Bullshit. There are a lot of instructions that not only execute in 1 second, it can sometimes do several of the same instruction at once.
Obvious typo is obvious: 1 clock != 1 second. 4.0 GHz = 4 billion clocks per second.


It does appear I was backwards...assuming no cache misses; that's the point though, isn't it? With two threads in the core, more usually gets done. The difference between HTT and Bulldozer's implementation is that Bulldozer should theoretically (assuming all else was equal) be able to do more integer operations in the same time frame. That still doesn't change the definition of a core.

I have no problem with Bulldozer's design. I have a problem with AMD calling it 8-cores (except where appropriate in some Opterons).


I find it ironic K10 beats Bulldozer on pretty much every one. The only advantage Bulldozer has over K10 is the higher clockspeeds.
 
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Obvious typo is obvious: 1 clock != 1 second. 4.0 GHz = 4 billion clocks per second.
My bad, I corrected it.
It does appear I was backwards...assuming no cache misses; that's the point though, isn't it? With two threads in the core, more usually gets done. The difference between HTT and Bulldozer's implementation is that Bulldozer should theoretically (assuming all else was equal) be able to do more integer operations in the same time frame. That still doesn't change the definition of a core.
The point is that overall poor performance is due to a slim core, not a shared module and the throughput of BD in my last post is a very clear indicator of that.
I find it ironic K10 beats Bulldozer on pretty much every one. The only advantage Bulldozer has over K10 is the higher clockspeeds.
Clock wise, K10 was a significantly larger core but, it also had a lot more under the hood dedicated for one core. I'll give AMD that they were able to squeeze quite a bit of parallel throughput on these CPUs but that's never the kind of workload consumers really need to care about.

The simple fact is that BD has two real cores, the problem is that while uOps execute just as fast, instructions that have certain combinations of uOps is going to impact AMD's BD core a lot more than one of Intel's. Even Intel has shown that they would rather beef up a core and AMD's problem is that two lanky cores isn't going to provide the single-threaded throughput you want. If there are instructions that are taking fewer cycles to complete on Intel CPUs, that's a pretty tell tale sign that it's the cores themselves. Add to that the fact that BD cores scale almost linearly on purely parallel workloads (excluding certain FP applications but, that really depends on the particular instructions being used.)

Nothing here to me says they're not 8 real cores. What people are pissed off about is that they're 8 gimped cores, even for integer operations but, that's not because of shared components. If it was a real implementation of hardware SMT like hyper-threading, we wouldn't see the kind of scaling we're seeing with modules which is near linear for purely parallel workloads. What we're seeing is 8 core CPUs where every core is something like 80% of what it should be. It scales properly and runs properly, with the exception that single threaded performance is 20% less than where it should have been and that people were expecting Phenom II like performance in single-threaded applications but BD performance on multi-threaded applications which wasn't the result.

AMD made some choices and it resulted in focusing on more cores and less on individual core performance. As a result, people got irritated that their skinny cores couldn't bite off enough at once and wanted their fatter cores that were more efficient in single threaded applications back (here comes Xen!)

Our disagreement isn't that Bulldozer blows, it's how it blows, and I think blaming the FPU and shared components is a bit of a stretch given the amount of information that indicates that even integer performance is tailing K10 per clock. They only try to make up for that with clock speeds, as you said. None of this has to do with whether it has 8 real cores or not, it has to do with how shitty the slimmed down integer cores are. Mix that with the shared FPU and added latencies on FP instructions, and you have a recipe lackluster performance. All of which still can happen even if there are 8 real cores.

Take Intel's 8c Atom the C2750 I think it is. It's performance trails core series CPUs at the same clock speed with half as many cores but with SMT, so does it mean that the Atom doesn't have real cores? NO! It means the Atom's core is lacking in performance despite having 8 real cores and doesn't efficiently use every clock cycle like the i5 and i7s, just like Bulldozer.
 

eidairaman1

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Good Point, Yea I did a CPU z comparison of the 8350 vs Intel, the Intel parts lead AMD by 8% in Single Thread Performance. 16vs24. the OCing of the BD only pushes its multithread performance up.

My bad, I corrected it.

The point is that overall poor performance is due to a slim core, not a shared module and the throughput of BD in my last post is a very clear indicator of that.

Clock wise, K10 was a significantly larger core but, it also had a lot more under the hood dedicated for one core. I'll give AMD that they were able to squeeze quite a bit of parallel throughput on these CPUs but that's never the kind of workload consumers really need to care about.

The simple fact is that BD has two real cores, the problem is that while uOps execute just as fast, instructions that have certain combinations of uOps is going to impact AMD's BD core a lot more than one of Intel's. Even Intel has shown that they would rather beef up a core and AMD's problem is that two lanky cores isn't going to provide the single-threaded throughput you want. If there are instructions that are taking fewer cycles to complete on Intel CPUs, that's a pretty tell tale sign that it's the cores themselves. Add to that the fact that BD cores scale almost linearly on purely parallel workloads (excluding certain FP applications but, that really depends on the particular instructions being used.)

Nothing here to me says they're not 8 real cores. What people are pissed off about is that they're 8 gimped cores, even for integer operations but, that's not because of shared components. If it was a real implementation of hardware SMT like hyper-threading, we wouldn't see the kind of scaling we're seeing with modules which is near linear for purely parallel workloads. What we're seeing is 8 core CPUs where every core is something like 80% of what it should be. It scales properly and runs properly, with the exception that single threaded performance is 20% less than where it should have been and that people were expecting Phenom II like performance in single-threaded applications but BD performance on multi-threaded applications which wasn't the result.

AMD made some choices and it resulted in focusing on more cores and less on individual core performance. As a result, people got irritated that their skinny cores couldn't bite off enough at once and wanted their fatter cores that were more efficient in single threaded applications back (here comes Xen!)

Our disagreement isn't that Bulldozer blows, it's how it blows, and I think blaming the FPU and shared components is a bit of a stretch given the amount of information that indicates that even integer performance is tailing K10 per clock. They only try to make up for that with clock speeds, as you said. None of this has to do with whether it has 8 real cores or not, it has to do with how shitty the slimmed down integer cores are. Mix that with the shared FPU and added latencies on FP instructions, and you have a recipe lackluster performance. All of which still can happen even if there are 8 real cores.

Take Intel's 8c Atom the C2750 I think it is. It's performance trails core series CPUs at the same clock speed with half as many cores but with SMT, so does it mean that the Atom doesn't have real cores? NO! It means the Atom's core is lacking in performance despite having 8 real cores and doesn't efficiently use every clock cycle like the i5 and i7s, just like Bulldozer.
 

Aquinus

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Good Point, Yea I did a CPU z comparison of the 8350 vs Intel, the Intel parts lead AMD by 8% in Single Thread Performance. 16vs24. the OCing of the BD only pushes its multithread performance up.
Then on multi-threaded score it only starts to catch up when the Intel CPU starts relying on hyper threading which goes back to "if they're not real cores, why do they scale like they are?"
 
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