Modern motherboards with 6+ usable PCIe slots?

[dragontamer5788]

Which is why PCIe 5.0 makes no sense in the desktop space. Instead of giving us 28 lanes of PCIe 5.0, gives us 40 of PCIe 4.0.

I mean, USB4 is 40Gbps (~4GBps practical) and USB 3.2 2x2 is 10Gbps (~1GBps practical).

That means the Mouse and Analog Capture Cards **should** be USB these days. Even 10Gbps SFP+ could be USB in theory (though I'm not aware of any USB to SFP+ port yet). https://www.amazon.com/Elgato-Video-Capture-Digitize-iPad/dp/B0029U2YSA

USB is the typical consumer expansion port, in practice. The 1Gbps to 10Gbps from typical USB ports (let alone from the newest USB4 or USB3 2x2 standards) are more than enough to handle the typical consumer application.

 

[Wirko]

USB is the typical consumer expansion port, in practice. The 1Gbps to 10Gbps from typical USB ports (let alone from the newest USB4 or USB3 2x2 standards) are more than enough to handle the typical consumer application.

That's it. The number, speed, and usability of USB ports has been growing steadily, and the portability of USB peripherals is sometimes a plus.

 

[chrcoluk]

A gen 5 platform can still have lower gen slots.

Here is the layout of my Z690 board. None of these slots are shared either, can all be used at once with nothing else on board getting disabled.

Slot 1 - Gen 3x1 Chipset - unused, might add an i210 nic here.
Slot 2 - Gen 5x16 CPU - used by GPU.
Slot 3 - Gen 4x4 Chipset - unused.
Slot 4 - Gen 3x1 Chipset - used by discrete sound card.
Slot 5 - Gen 3x4 Chipset - used by DC P4600 SSD.

Bifurcation is choice of manufacturer I expect it isnt that hard to implement, so this board could clearly have more slots, simply by changing one of the x4 to multiple x1.

Now I look at Z690 design and Raptor Lake CPU design.

CPU has 24 PCIE lanes split into 16 direct, and 8 to chipset.

So second way this board can get 6th slot is the old method which was very common in past generations to have 2 slots routed from CPU that share the 16 lanes.

So new layout would be.

Slot 1 - Gen 3x1 Chipset
Slot 2 - Gen 5x16(8) CPU
Slot 3 - Gen 5x8 CPU
Slot 4 - Gen 4x4 Chipset
Slot 5 - Gen 3x1 Chipset
Slot 6 - Gen 3x4 Chipset

Z690 has 12 4.0 lanes and 16 3.0 lanes. 28 lanes total. The lanes has an asterisk next to it, which I dont know what it means though. But on my board only 4 of those 12 gen 4 lanes are allocated to one pcie slot, and only 6 of those 16 gen 3 lanes allocated to slots.

No magic needed, just a different design direction.

What Assimilator said isnt magic, just reality of different design decisions made in the past.

What is happening now is decisions being made to route many of these lanes to M.2 slots which also take up valuable PCB space in the area pcie slots would be placed on a board. This to me stems from the decision to go M.2 on consumer desktop boards. Likely market segmentation related.

--edit, added way I currently utilising slots to post.