AMD's Future Ryzen SoCs May Feature New Chip-Stacking Technology

[Nomad76]

AMD has recently filed a patent revealing plans to implement "multi-chip stacking" in future Ryzen SoCs, as Wccftech reports, quoting a post on X from @coreteks: "New patent from AMD shows how future Zen SoCs could look. Basically a novel packaging design that enables compact chip stacking and interconnection by having them partially overlap, as in this figure. The dotted line is a larger die stacked on top of those smaller ones". The patent details a new approach where smaller chiplets partially overlap with a larger die, creating space for additional components and functions on the same die. This strategy aims to improve the efficiency of the contact area, thus making room for higher core counts, larger caches, and increased memory bandwidth within the same die size. The proposed stacking will reduce the physical distance between components through overlapping chiplets, thus minimizing interconnect latency and achieving faster communication between different chip parts. The design will also improve power management, as the segregated chiplets allow for better control of each unit through power gating.

Even if long-time rival Intel has lost some of its momentum (and market share) this year, AMD's chance to push ahead with its intention to become number one in the market is to continue to innovate. In the same way that its 3D V-Cache technology made the X3D processor lineup so successful, this chip stacking approach could play a major role in future AMD Ryzen SoCs. It seems that AMD is committed to moving away from the monolithic design era and taking the road of multi-chiplet; however, it can be a long wait until (and if) this chip stacking will complete the journey from patents to design, production, and final product.



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[Panther_Seraphin]

This could be a massive leap from Infinity fabric and would be interesting to see if they could do a larger IO Die with things like quad channel memory or more CUs to rival things like quicksync while leaving enough space for CCDs to connect via TSVs which will hopefully eliminate the latency penalty that the current chiplet design suffers from by going through the substrate.

I would also wonder if it means things like NPUs/Accelerators could be interchanged to maximise the product stack across the differing markets. So you could have for example one part with 6 CCDs and 2 Accelerators and another with 2 CCDs and 6 accelerators and everything in between. With AMD moving to chiplet design in GPU as well, perhaps that could be a third option for those stacks.

ROCm needs to be AMDs focus in the short to mid term software wise to start taking some market share from nVidia and to make their CPUs have a real USP over an equivalent Intel.

 

[tommo1982]

Before it reaches consumer market, if ever, it will be introduced in servers first. Certainly it will increase price and considering how PCIe 5.0 increased pc hardware prices in general, the genral consumer has no need for such thing.

 

[ymdhis]

Yeah, this was mentioned on videocardz one or two weeks ago. Basically they are extrapolating the 9800X3D 3d stacking. The 9800X3D has the memory on bottom and CPU cores on the top for heat reasons. This has several components on the bottom and presumably the most heat intensive parts will go on top. Someone mentioned that the upcoming Halo APUs after Strix Halo will use this. Put cache and cpu cores on the bottom, and a giant GPU on top of them all, to minimize latency for the cache, which the memory starved GPU really really needs.

The one big problem with chiplets was that the interconnects had latency issues and consumed a lot of power, which is why high-end chiplet RDNA3 GPUs did not perform well, to the point that the RDNA4 equivalents have been cancelled. This seeks to improve on those.

What all that in mind, this may not help a lot for CPUs, but it can be one hell of a huge step for GPUs and APUs.... in 2026-7.

 

[Dr. Dro]

I wonder if full 3D integration is still too costly or unfeasible for desktops. Perhaps they don't quite meet performance targets yet. Intel certainly seems to have greatly delayed/indefinitely postponed their implementation, and AMD certainly seems in no rush to abandon the chiplet design, opting to further refining it instead.

 

[R0H1T]

I don't see the overlap, where is it?

 

[qcmadness]

I wonder if full 3D integration is still too costly or unfeasible for desktops. Perhaps they don't quite meet performance targets yet. Intel certainly seems to have greatly delayed/indefinitely postponed their implementation, and AMD certainly seems in no rush to abandon the chiplet design, opting to further refining it instead.

Ask Intel.

 

[Readlight]

Can't understand this part drawing.
Maybe doted line chip is backside

 

[ymdhis]

Can't understand this part drawing.
Maybe doted line chip is backside

The dotted line is a large chip, sitting on top of smaller chiplets. Think of the chiplets being pillars holding up the ceiling that is the GPU.

 

[SL2]

Maybe doted line chip is backside

Maybe read the text lol

The dotted line is a larger die stacked on top of those smaller ones

 

[TechLurker]

If AMD can also integrate the built-in CPU micro-liquid cooling tech that had a major breakthrough a few years ago, they could help better manage heat and still provide gains, using the bare areas between chiplets for cooling channels and connecting to the IHS.

 

[ZoneDymo]

Title of this article just annoys me, like clickbait youtube videos:

"AMD's Future Ryzen SoC's May Feature New Chip-Stacking Technology"

Wow so future stuff might use new tech??!!? unheard off, usually future stuff uses old tech.....

 

[Daven]

Cache on the bottom, Zen dense cores in the middle and Zen classic cores on top. Sounds like the perfect chip sandwich. Put a dozen of those on package and you have yourself a party platter.

 

[SL2]

Title of this article just annoys me, like clickbait youtube videos:

"AMD's Future Ryzen SoC's May Feature New Chip-Stacking Technology"

Wow so future stuff might use new tech??!!? unheard off, usually future stuff uses old tech.....

Not really. This is not just new tech in the broadesst of terms, it points directly to a specific patent (which I haven't bothered looking up).

Remove the word "future" and you just add confusion.

A bait would be: "AMD's insane new chip-stacking - Intel is doomed*?"


*I'm not saying it already is/isn't

Give Nomad a break ffs

 

[kondamin]

The one big problem with chiplets was that the interconnects had latency issues and consumed a lot of power, which is why high-end chiplet RDNA3 GPUs did not perform well, to the point that the RDNA4 equivalents have been cancelled. This seeks to improve on those.

I think it’s more of a tsmc can only produce so much of the stuff and nvidia gobbled it all up.
same happened to hbm

 

[Dr. Dro]

Ask Intel.

My question was more generic in nature. I feel pretty horrible right now so excuse me if I worded things poorly, what I meant to say is that neither Intel nor AMD have released a fully integrated 3D packaged x86 SoC since Lakefield (largely a prototype), and neither seem to be planning on doing so imminently.

The way I interpreted this news post is that they'll be using something like CoWoS to essentially "bond" the chiplets together through an interposer which will essentially serve the purpose of interconnect, achieving monolithic-like access speeds across chiplets or very close to it, somewhat like an immensely high bandwidth ring bus?

 

[londiste]

This could be a massive leap from Infinity fabric and would be interesting to see if they could do a larger IO Die with things like quad channel memory or more CUs to rival things like quicksync while leaving enough space for CCDs to connect via TSVs which will hopefully eliminate the latency penalty that the current chiplet design suffers from by going through the substrate.

Why would that change something significantly in terms of Infinity Fabric? They'll run IF over silicon an TSVs or something but it will still be IF. The latency penalty has quite a bit to do with distance and less about going over substrate. Power is a different thing though.

My question was more generic in nature. I feel pretty horrible right now so excuse me if I worded things poorly, what I meant to say is that neither Intel nor AMD have released a fully integrated 3D packaged x86 SoC since Lakefield (largely a prototype), and neither seem to be planning on doing so imminently.

Isn't Arrow Lake today doing precisely that and same as Lakefield? It is chiplets/tiles over a silicon interposer. Today from what we know it still seems to be a passive interposer though.

The way I interpreted this news post is that they'll be using something like CoWoS to essentially "bond" the chiplets together through an interposer which will essentially serve the purpose of interconnect, achieving monolithic-like access speeds across chiplets or very close to it, somewhat like an immensely high bandwidth ring bus?

There does not seem to be much out there about what the patent is actually about. Is it the partial overlap? I am struggling a bit to see the significance of that. Size and yield considerations for the interposer maybe?

 

[Wirko]

Cache on the bottom, Zen dense cores in the middle and Zen classic cores on top. Sounds like the perfect chip sandwich. Put a dozen of those on package and you have yourself a party platter.

Wow, and its performance will be measured in pizzas per minute that it can bake! PPM!

 

[Aquinus]

AMD put the 3d v cache under the CCDs for current gen to get around the heat flux problem with heat having to travel through the cache. If we're stacking logic on top of eachother, how do they intend to solve the heat problem? Any logic sandwiched between other logic circuits are going to get very hot.

 

[freeagent]

I also suspect they buried the cache so that they didn't have to use prime silicon to lower thermals.

This should be pretty interesting.