R3D: That's an elegant way of saying that you won't support CUDA, in spite of nVidia's claims that you could/should/must. 
Eric: Irrespective of what nVidia says, the truth is that CUDA is their proprietary solution, which means that if we were to use it we'd be stuck being second place and following their lead; that's not really a position we want to be in. Another characteristic of CUDA is that it's very G80 centric, so first we'd have to build a G80 in order to have a reason to use CUDA. So, no, we're not going to support/use CUDA in any foreseeable future.
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R3D: On the topic of tessellation, when are we going to see the tessellation SDK and/or documents detailing how to leverage the tessellator? Those are pretty much non-existent in public form as far as I know.
Eric: Hmm, that's an interesting question. The tessellation SDK is not yet done, and there's no firm date for its release at this point in time. We're working with interested developers directly. Driver support is also not yet completely finalized, we plan to introduce it in the November 8.11 Catalysts. So you'll have to wait just a little bit more before you can start playing with it.
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R3D: How is the Edge-Detection part done for Edge-Detect AA? Is it purely analytical, e.g. based on applying a Sobel/Canny-Deriche filter, or using differential edge detection, or do you rely on Z-compares/checking whether a tile is fully compressed or not?
Eric: We don't want to reveal too much about our algorithm, it's a secret sauce of sorts. But in a nutshell, it's a mixture of hardware and software, and it uses a technique to do coarse edge location and isolate the regions of the screen that contain edges, and then applies a filter on these areas to do fine location of the edges. Then an adaptive kernel filter is applied for the resolve that is location and edge aware.
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R3D: Further elaborating on this topic, where does the difference between the 4870 and the 4870X2 stem from? The X2 downclocks to 507/500 at idle, whilst the 4870 does not downclock the memory at all ... since they're both GDDR5 parts, it can't be GDDR5 related, can it?
Eric: Lower speed GDDR5 modules are in the works, so it's not an inherent GDDR5 limitation. Having said that, the trouble with GDDR5 at clocks below the 500MHz mark is that you have to shift the operating mode towards a more GDDR4-like one. This requires some software work to be done. With the 4870 we didn't do it since other things took precedence, and because we were already getting good thermal and power characteristics. The 4870's power draw is in line with what you'd expect from a performance part. On the other hand, for the 4870X2 we had to deal with having what is practically 2 4870s on the same PCB, with an extra 1GB of RAM, so we implemented a more aggressive downclocking. With that in mind, we are looking at changing the way the 4870 behaves and having a similar clocking strategy for it, but that requires implementing certain changes in the software stack, and it's not the primary priority currently, since the card has characteristics that are within the envelope that is specific to the segment it targets.
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R3D: Now that we've started touching sensitive topics, can we find out what's up with the interconnect? Why is it disabled? Are naysayers correct in stating that it's up to the AIB whether or not the traces for it get built into the PCB, and that it's likely to not be enabled?
Eric: The sideport interconnect is fully functional in the reference design. Though we've found that with the current AFR mode of multi-GPU support, the additional bandwidth brought by the interconnect does not translate to a significant improvement in performance. However, we are continuously working on optimizing how our ATI CrossFireX (tm) technology scales and trying different methods, and could decide to enable the sideport if a method is found which gives better results and benefits from it.
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R3D: Now that we've started touching sensitive topics, can we find out what's up with the interconnect? Why is it disabled? Are naysayers correct in stating that it's up to the AIB whether or not the traces for it get built into the PCB, and that it's likely to not be enabled?
Eric: The sideport interconnect is fully functional in the reference design. Though we've found that with the current AFR mode of multi-GPU support, the additional bandwidth brought by the interconnect does not translate to a significant improvement in performance. However, we are continuously working on optimizing how our ATI CrossFireX (tm) technology scales and trying different methods, and could decide to enable the sideport if a method is found which gives better results and benefits from it.
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