Theory of DDR3 Voltage Limitations for Bloomfield Gains Ground

[Morgoth]

Nehalem supports single, dual, triple

 

[InnocentCriminal]

\m/

Triple w00!



That is all... for now.

 

[DaMulta]

So for chips is dual then? And 5 sticks will be still dual channel maybe.

I'm just wonder I can't find any links yet about it.

Also been looking for what happens when you stick 3 sticks in on current motherboards. But I think that he is right that one stick will not be in dual channel. AMD XP chips had motherboards with 3 slots and it would run in dual channel mode.

 

[DaMulta]

While doing my digging I found this about the old nforce2 and it using 3 chips for dual channel. I'm guessing 5 could do the same thing.
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=1719&p=4

This is the new Intel
http://www.sysopt.com/features/cpu/article.php/3775041

The onboard memory controller of the Core i7 platform supports the de facto single and dual-channel DDR3 architecture, but adds a new wrinkle: triple-channel memory. This announcement lit up some eyes in the enthusiast community, and although Intel has been quiet in terms of performance results, demo sessions have yielded some very impressive visual scores.

The first Nehalem iteration is rumored to implement a triple-channel DDR3 architecture, and now that the CPU determines the memory type, speed, capacity, and number of modules, this is going to put some limitations on both motherboard vendors and end users. For example, existing DDR3 memory kits are sold in a dual-channel format, with two modules. The Intel X58 requires three modules for top performance, and many potential upgraders are waiting for memory manufacturers to introduce their triple-channel kits, featuring a trio of fully matched and guaranteed DDR3 sticks.

The presence of an integrated memory controller also means that the Northbridge components of the X58 chipset will be greatly simplified. Intel will even release a Core i7 processor with an integrated graphic core, further limiting the role of the chipset in this new architecture. The Nehalem also marks the debut of Intel's QuickPath Interconnect, with each bidirectional link supplying up to 12.8GB/sec of bandwidth each way for a total bandwidth of 25.6GB/sec per link -- that's over 50GB/sec for the top-end models that will have two QuickPath links.

cool, you never know they could of taken out dual, but that would be a crazy thing to do.




Edited:thought about what it said.
I feel like an idiot wondering about these things, lol So it does have dual channel support . I was talking to someone else that wondered the same thing. So if you put 4 chips in that triple channel motherboard what happens. I wonder if you put 4 in will it still be in triple mode like it was dual mode for 3 chips on the older nforce2.

I think it's rambus ram that made me think it. Because in that system you had to have 2 chips. If you didn't it didn't work, but of course DDR is different.

 

[DaMulta]

Am I going to far with this lol.

I could test the 3 sticks in my machine tonight sometime.

 

[Morgoth]

i can also test it on my i got 4 gigs in my p4
if you like to

 

[Wile E]

Here ya go D. 3 sticks in an X38 board.

 

[DaMulta]

BTW if anyone was wondering his SS is of DDR2 not DDR3.



Cool, so with the new Intel it should be triple channel if you just bought two sets 2 DDR3 chips.

 

[spud107]

could have one stick as backup lol.

 

[DaMulta]

could have one stick as backup lol.

What would be the point if it's still running in triple channel?

 

[kid41212003]

Here ya go D. 3 sticks in an X38 board.

Is that your board and memory? I think It might be 2x1GB and 2x512MB...

 

[Wile E]

Is that your board and memory? I think It might be 2x1GB and 2x512MB...

Yes, it's my board and memory. It's 2x1GB Transcend aXeRam 1200 and 1x1GB Crucial Ballistix 800, for a total of 3x1GB sticks.

 

[Fitseries3]

remember that garbage that the core voltage is directly linked to the ram voltage?

myth dispelled....

give me a min to explain.....

QPI/dram voltage is related to the path between the memory controller and the actual ram itself. this needs to be within .5v of the vcore to prevent damage to the memory controller.
Dram bus voltage is the actual voltage that the ram is running at.... IE: Vdimm, Vram, Vmem, etc. this should be as close as possible to within .5v from the qpi/dram voltage.

While Asus and Intel (rightly) scare everyone (read: uneducated) into thinking that 1.65V on the DRAM voltage should be the absolute limit before you reach for the fire-blanket, all that's really needed it to obey this: keep the CPU uncore voltage within 0.5V difference of the DRAM voltage and there's no problem. Over this potential difference and you’ll greatly increase the chance of CPU death, but it certainly won't happen instantly in a big ball of fail fire if you make a mistake.

source.... http://www.bit-tech.net/hardware/2008/11/06/overclocking-intel-core-i7-920/3

and if you think 2000mhz isnt possible on x58....

here ya go.........

2XXXmhz ram on x58 in tripple channel.

 

[Scrizz]

remember that garbage that the core voltage is directly linked to the ram voltage?

myth dispelled....

give me a min to explain.....

QPI/dram voltage is related to the path between the memory controller and the actual ram itself. this needs to be within .5v of the vcore to prevent damage to the memory controller.
Dram bus voltage is the actual voltage that the ram is running at.... IE: Vdimm, Vram, Vmem, etc. this should be as close as possible to within .5v from the qpi/dram voltage.



source.... http://www.bit-tech.net/hardware/2008/11/06/overclocking-intel-core-i7-920/3

and if you think 2000mhz isnt possible on x58....

here ya go.........

2XXXmhz ram on x58 in tripple channel.

thx

 

[Sasqui]

^ ditto - real screenies excite me, specially over 4GHZ!!!!