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K8L details continue to pour in at AMD's Technology Analyst Day - AMD's CTO Phil Hester was specific to refer to these new technologies as simply "new architecture," and never using the K8L core name.
A major push for AMD's K8L design is in "modular" component design - meaning everything from L3 cache to memory controllers are developed as individual components and linked together with reusable, robust designs. To some extent, processor design is already modular with libraries and designs that are developed individually. However, Hester insists this new modular approach takes this modular approach even further, claiming that the company is developing "better define the interfaces for each of these building blocks."
Additionally, Hester revealed some more information about the cache specifics on K8L. Each K8L core will have 64KB of dedicated L1 cache, followed by 512KB of dedicated L2 cache. The base models of K8L will have 2MB of shared L3 cache, but Hester also went on to claim that adding more L3 cache was in the company's roadmap. One thing AMD representatives have not particuarly touched on is the cache reduction from 64+64KB (data+instruction) to 32+32KB. AMD employees have assured us this move is logical with the addition of L3 cache.
View at TechPowerUp Main Site
A major push for AMD's K8L design is in "modular" component design - meaning everything from L3 cache to memory controllers are developed as individual components and linked together with reusable, robust designs. To some extent, processor design is already modular with libraries and designs that are developed individually. However, Hester insists this new modular approach takes this modular approach even further, claiming that the company is developing "better define the interfaces for each of these building blocks."
Additionally, Hester revealed some more information about the cache specifics on K8L. Each K8L core will have 64KB of dedicated L1 cache, followed by 512KB of dedicated L2 cache. The base models of K8L will have 2MB of shared L3 cache, but Hester also went on to claim that adding more L3 cache was in the company's roadmap. One thing AMD representatives have not particuarly touched on is the cache reduction from 64+64KB (data+instruction) to 32+32KB. AMD employees have assured us this move is logical with the addition of L3 cache.
View at TechPowerUp Main Site
