MSI Calls Bluff on Gigabyte's PCIe Gen 3 Ready Claim

[Steven B]

no when there no device in second slot the lanes are directed toward slot 1 for full 16x. The whole does with having lanes directly connected is because it saves money on switches that aren't needed.

 

[neliz]

no when there no device in second slot the lanes are directed toward slot 1 for full 16x. The whole does with having lanes directly connected is because it saves money on switches that aren't needed.

Again, please show in that picture where the 16 lanes are coming from. I see 8 from CPU and 8 from switch. If you want I cqn look for higher res shots and highlight the traces for you.

If traffic passes through the switches, its gen2, simple as that.

 

[n-ster]

Gigabyte's wording was "Gen3 maximum bandwidth" which would be 32GB/s not 16GB/s

AFAIK, the wording was

as well as offer native support for PCI Express Gen. 3 technology, delivering maximum data bandwidth for future discrete graphics cards

which does not mean maximum bandwidth of PCI-E 3.0 IMO

 

[neliz]

AFAIK, the wording was

which does not mean maximum bandwidth of PCI-E 3.0 IMO

the maximum data bandwidth of the upcoming graphics cards is ~32GB/s as far as I know.
Maximum in that sentence refers to the graphics card and not the maximum of the motherboard.

The fact that you and I can't agree on what the wording means makes it clear for me that Gigabyte intended on misleading the consumer to thinking the boards support 32GB/s, or as they put it "maximum data bandwidth for future discrete graphics cards "

 

[n-ster]

it says DISCRETE graphic cards

 

[neliz]

it says DISCRETE graphic cards

No, it doesn't

go to the GBT site and read.

future discrete graphics cards

See, you missed an S there

Now, again, I'll type slowly, maybe that will help.

They say FUTURE DISCRETE GRAPHICS CARDS and hint at for instance AMD's Radeon 7000 serie or NVIDIA's Geforce 600 series.
These cards are rumored (or confirmed already?) to have PCI Express 3.0 x16.
That means ~32GB/s maximum data bandwidth (gigacheat's own words)

NOW
THE LINK

Putting a PR statement out that your motherboards offer delivering maximum data bandwidth in correlation with Gen3 compatibility and Gen3 graphics cards at least to me seems like they are talking about the same thing, Gen3 x16.

 

[TheLostSwede]

I think the multiple meaning in this case refers to the fact that there are more than one company that makes cards, not so much that you'll be able to run more than one card in the boards, but whatever...
Interpreting written language is an art, just ask all those people that have a different opinion about what it says in all the "holy" books out there... wars have been started over it so hey...

 

[dazz]

when the second pci-e slot is NC the SW is OFF so all the PCI-e lanes are directly connected to the CPU.

no when there no device in second slot the lanes are directed toward slot 1 for full 16x. The whole does with having lanes directly connected is because it saves money on switches that aren't needed.

Neliz is right for all I know. The switches work multiplexing 8 lanes, so depending on the slot configuration you have those 8 lanes connected (switched) to slot 1 (only 1st slot populated @ 16x) or slot 2 (both slots populated @ 8x8x), but always through the switch cause that's how the lanes are wired.
In motherboards with no SLI/XFire support where there's only one PCIe 16x slot, there's no need for switches and all 16 lanes are hardwired to the 16x slot. Those may work at full 3.0 speeds if the capacitors and resistors don't need to be upgraded too, but then again who needs PCIe 3.0 in single GPU setups. The 4x slot gets it's bandwidth from the PCH / DMI connection if I'm not wrong

But that is not possible. what will happen is that the primary slot will only get x8 link that is PCIe 3.0, and the other 8 lanes will not be capable of 3.0 due to the board's hardware in the link. This may create situation where the slot defaults to PCIe 1.0, or perhaps 2.0, because of the lane confusion.


TBH, I'm not sure, exactly, what will happen with these boards and the primary slot. It's not as simple as it seems.

That's what I would like to know too, but if it's posible to have one slot at 8x PCIe 3.0 and the second at 8x PCIe 2.0 in SLI/XFire, you already have a 50% extra BW theoretically in multi GPU setups where it may help someday.
I mean, if you can have TRI-SLI setups at 16x8x8x, it should be possible to have that too since it's different slots at different speeds, not different lanes in the same slot at different speeds

 

[n-ster]

No, it doesn't

go to the GBT site and read.



See, you missed an S there

Now, again, I'll type slowly, maybe that will help.

They say FUTURE DISCRETE GRAPHICS CARDS and hint at for instance AMD's Radeon 7000 serie or NVIDIA's Geforce 600 series.
These cards are rumored (or confirmed already?) to have PCI Express 3.0 x16.
That means ~32GB/s maximum data bandwidth (gigacheat's own words)

NOW
THE LINK

Putting a PR statement out that your motherboards offer delivering maximum data bandwidth in correlation with Gen3 compatibility and Gen3 graphics cards at least to me seems like they are talking about the same thing, Gen3 x16.

the future discrete GPUs will not utilize more than PCI-E 3.0 x8 for sure. Just because USB 3 is capable of 4Gbps, doesn't mean a USB 3 flash drive will use the 4Gbps. There are SATA 6Gbps HDDs, but these HDDs don't even max out SATA 3Gbps!!! A future DISCRETE graphics card is not going to be using more than 16Gbps, that is for sure, so you are getting maximum data bandwidth for future DISCRETE GPUs!

 

[jfk1024]

Again, please show in that picture where the 16 lanes are coming from. I see 8 from CPU and 8 from switch. If you want I cqn look for higher res shots and highlight the traces for you.

If traffic passes through the switches, its gen2, simple as that.

so... you are saying that when the second pci-e slot is NC the data is sent from the CPU to the first 8 lanes and also the data is sent through the pci-e switch to the last 8 lanes?

 

[cadaveca]

so... you are saying that when the second pci-e slot is NC the data is sent from the CPU to the first 8 lanes and also the data is sent through the pci-e switch to the last 8 lanes?

Yes, that is it, exactly. So, how is there any slot with real PCIe 3.0 on a board that does not have these PCIe 3.0 switches, and offers both x16 and x8/x8?

Will these board do PCIe 3.0 x8 to the first slot only? Or will they report PCIe 3.0, but not actually be doing PCIe 3.0? And how does that work with the second slot?


I do not know how this will work. I need PCIe 3.0 CPUs and VGAs before I can comment on what's really gonna happen here, and neither are expected, that i know of, in the next 6 months.

 

[dazz]

so... you are saying that when the second pci-e slot is NC the data is sent from the CPU to the first 8 lanes and also the data is sent through the pci-e switch to the last 8 lanes?

that's how I understood it

 

[dazz]

Yes, that is it, exactly. So, how is there any slot with real PCIe 3.0 on a board that does not have these PCIe 3.0 switches, and offers both x16 and x8/x8?

Will these board do PCIe 3.0 x8 to the first slot only? Or will they report PCIe 3.0, but not actually be doing PCIe 3.0? And how does that work with the second slot?


I do not know how this will work. I need PCIe 3.0 CPUs and VGAs before I can comment on what's really gonna happen here, and neither are expected, that i know of, in the next 6 months.

I really have no idea, but again, I'm guessing at least in dual GPU setups, having the first slot at 8x 3.0 and the second (the switched one) at 8x 2.0 makes sense (unless new resistors and capacitors are needed as MSI says)
After all it's not uncommon to have different slots at different speeds in TRI-SLI scenarios like in X58 at 16x8x8x

 

[neliz]

that's how I understood it

http://cdn1.techbang.com.tw/system/...c12cec39928b4abd3539cd23d57eec.png?1313086800

Thanks Dazz! that picture is more clear than anything I can paint.exe

 

[jfk1024]

that's how I understood it

http://cdn1.techbang.com.tw/system/...c12cec39928b4abd3539cd23d57eec.png?1313086800

So a motherboard with a single pci-e connected directly to the CPU it is a PCI-e 3.0 ready motherboard, right?

 

[jfk1024]

http://www.gigabyte.com/press-center/news-page.aspx?nid=1048

" * The specifications are subject to change without notice. "

 

[neliz]

So a motherboard with a single pci-e connected directly to the CPU it is a PCI-e 3.0 ready motherboard, right?

No, not necessarily as it still lacks the required capacitors and resistors required by Intel for Gen3 validation.
Short version: No

 

[dazz]

So a motherboard with a single pci-e connected directly to the CPU it is a PCI-e 3.0 ready motherboard, right?

I'm not an expert on the matter, so take what I say with a grain of salt, but it looks like unless there's something else in the circuitry apart of the switches (like those resistors and capacitors) that needs upgrading to achieve 3.0 speeds, then yes, those boards with a single 16x slot should be PCIe 3.0 ready. But with just one GPU the PCIe bandwidth shouldn't be an issue at all for a long time, even in dual SLI/Xfire setups it's very unlikely that PCIe 2.0 BW will be a limiting factor with Kepler or AMD's 7000 series.

 

[neliz]

even in dual SLI/Xfire setups it's very unlikely that PCIe BW will be a limiting factor with Kepler or AMD's 7000 series.

And what if AMD/NV releases their professional parts or Compute oriented models first? BW requirements there are much bigger than in games.

 

[dazz]

And what if AMD/NV releases their professional parts or Compute oriented models first? BW requirements there are much bigger than in games.

obviously that would change everything. I guess there must be some applications right now that would take advantage of the increased BW, but not in gaming for now

And there's something else we may be overlooking: PCIe 3.0 power draw specs are up to 375W per slot (I think). Is current circuitry capable of that? maybe that's why the resistors and capacitors need upgrading? Will the controller be able to detect that and downgrade all the slots to 2.0 speeds with or without switches?

 

[neliz]

And there's something else we may be overlooking: PCIe 3.0 power draw specs are up to 375W per slot (I think). Is current circuitry capable of that? maybe that's why the resistors and capacitors need upgrading? Will the controller be able to detect that and downgrade all the slots to 2.0 speeds with or without switches?

No, PCI-SIG didn't change anything related to the power, so you'll still have your same limits.

The resistors and caps are there I think because of the increased frequency (signal integrity)

 

[dazz]

No, PCI-SIG didn't change anything related to the power, so you'll still have your same limits.

The resistors and caps are there I think because of the increased frequency (signal integrity)

Ok, thanks for the clarification.
Truth is I'm not too worried about this. I know I don't need PCIe 3.0... I'm much more concerned with the UEFI thing now! hope it's not true and I can upgrade to IB with my current P67 board if I want to.

 

[neliz]

Ok, thanks for the clarification.
Truth is I'm not too worried about this. I know I don't need PCIe 3.0... I'm much more concerned with the UEFI thing now! hope it's not true and I can upgrade to IB with my current P67 board if I want to.

I for one am not worried about this, in the past 15 years I've had zero problems doing complete firmware rewrites, microcode updates and BIOS reflashes on business PC's and Itanium servers.
Why would a slight increase from one version of UEFI to the other have more impact?

I just think gigabyte is trying to use some google translate errors there to feed media a scary story.

 

[Millennium]

I would hate to think I upgraded to sandy bridge for no reason. My main motivation was to be ready for Ivy Bridge. Damnit!

 

[jfk1024]

No, not necessarily as it still lacks the required capacitors and resistors required by Intel for Gen3 validation.
Short version: No

required by Intel? what is this? PCI-E specifications or Ivy bridge requirements?