Samsung Develops Industry's First 8 Gb LPDDR4 Mobile DRAM

[btarunr]

Samsung Electronics Co., Ltd., the world leader in advanced memory technology, announced today that it has developed the industry's first eight gigabit (Gb), low power double data rate 4 (LPDDR4), mobile DRAM.

"This next-generation LPDDR4 DRAM will contribute significantly to faster growth of the global mobile DRAM market, which will soon comprise the largest share of the entire DRAM market," said Young-Hyun Jun, executive vice president, memory sales & marketing, Samsung Electronics. "We will continue introducing the most advanced mobile DRAM one step ahead of the rest of the industry so that global OEMs can launch innovative mobile devices with exceptional user convenience in the timeliest manner."

Samsung's new high-speed 8Gb LPDDR4 mobile DRAM will provide the highest level of density, performance and energy efficiency for mobile memory applications, enabling end users to have faster, more responsive applications, more advanced features, and higher resolution displays while maximizing battery life.

The 8Gb LPDDR4 is fabricated on 20-nanometer (nm) class* process technology, and offers 1 gigabyte (GB) on a single die, which is the largest density available for DRAM components today. With four of the 8Gb chips, a single 4GB LPDDR4 package can provide the highest level of performance available today.

In addition, Samsung's new 8Gb LPDDR4 uses a Low Voltage Swing Terminated Logic (LVSTL) I/O interface, which was originally proposed by Samsung to JEDEC and has become a standard specification for LPDDR4 DRAM. Based on this new interface, the LPDDR4 chip will enable a data transfer rate per pin of 3,200 megabits per second (Mbps), which is twice that of the 20nm-class LPDDR3 DRAM now in mass production. Overall, the new LPDDR4 interface will provide 50 percent higher performance than the fastest LPDDR3 or DDR3 memory. Also, it consumes approximately 40 percent less energy at 1.1 volts.

With the new chip, Samsung will focus on the premium mobile market including large screen UHD smartphones, tablets and ultra-slim notebooks that offer four times the resolution of full-HD imaging, and also on high-performance network systems.

Samsung is leading mobile DRAM technology development and is the leader in mobile DRAM market share with its 4Gb and 6Gb LPDDR3. It started offering the thinnest and smallest 3GB LPDDR3 (6Gb) package solutions in November and will provide its new 8Gb LPDDR4 DRAM in 2014. The 8Gb mobile DRAM chip will rapidly expand the market for high-density DRAM in next-generation mobile devices.

View at TechPowerUp Main Site

 

[happita]

This article has nothing to do with desktops, but I see it as a step in the right direction since tablets and smartphones sales are growing exponentially over desktop PCs year by year. The earlier the adoption of DDR4 (whatever kind of iteration it may be) the better. I always welcome lower voltage while being the same performance, it saves us from extra unneeded heat expenditure

 

[NeoXF]

LPDDR is on like 32bit right? So in dual mode, 64bit... around 26GB/s at 3200Mbps? Also, while 40% less power at the same voltage is great, wasn't it supposed to lower voltage to begin with as well? I think desktop/SODIMM versions are supposed to run at less than that on average (0,95-1,2v).

 

[Aquinus]

LPDDR is on like 32bit right? So in dual mode, 64bit... around 26GB/s at 3200Mbps? Also, while 40% less power at the same voltage is great, wasn't it supposed to lower voltage to begin with as well? I think desktop/SODIMM versions are supposed to run at less than that on average (0,95-1,2v).

Where did you read that? Modern DDR3 is 64-bits per channel, LP or otherwise and I'm pretty sure that DDR2 was 64-bits wide per channel too.

I also wouldn't complain too loudly about less power usage at the same voltage. I suspect that means they would get even more when they start producing lower voltage ICs.

 

[NeoXF]

Where did you read that? Modern DDR3 is 64-bits per channel, LP or otherwise and I'm pretty sure that DDR2 was 64-bits wide per channel too.

I also wouldn't complain too loudly about less power usage at the same voltage. I suspect that means they would get even more when they start producing lower voltage ICs.

32bit processors that use LPDDR also use 32 bits per channel for it...Look it up.

Apple (or whoever designed their chips) used quad 32bit channel LPDDR2 in A6X and now they use single 64bit channel LPDDR3 in A7...
Qualcomm will use quad 32bit LPDDR3 in the future Snapdragon 805 SoC AND single 64bit channel LPDDR 2 or 3 in their upcoming first 64bit ARM SoC, Snapdragon 410.

 

[Aquinus]

Just because the DRAM is 64 bits wide (data bus) doesn't mean a 32-bit CPU can't address it. 32-bits is the address bus, not the data bus. 32-bit CPUs can address 32-bits of memory even if the memory has more then 32-bits worth of addresses. There is a difference between returning 64-bits of data and accessing data at an address in 64-bit space.
This might clarify things.

 

[NeoXF]

Just because the DRAM is 64 bits wide (data bus) doesn't mean a 32-bit CPU can't address it. 32-bits is the address bus, not the data bus. 32-bit CPUs can address 32-bits of memory even if the memory has more then 32-bits worth of addresses. There is a difference between returning 64-bits of data and accessing data at an address in 64-bit space.
This might clarify things.

Irrelevant unless there's a practical example, and I doubt anyone built a 32bit system for 64bits of memory adresses, outside of some old school 2P (and beyond) servers/workstations.

 

[Aquinus]

Irrelevant unless there's a practical example, and I doubt anyone built a 32bit system for 64bits of memory adresses, outside of some old school 2P (and beyond) servers/workstations.

Mobile devices are different considering you may only have one or two DDR chips (single ICs, not DIMMs) as opposed to at least 8 in one rank on a Computer DIMM. How many memory addresses DRAM and SRAM has depends on the size of the IC. It wouldn't make sense to pin out 32-bits or 64-bits worth of addresses if you're only going to use 28 of them (say for a 256Mbit chip). You would wire up 28 pins and leave the other 4 not connected (assuming one pin for every bit on the address bus.) Same way if you have the opposite problem. If you have a 64Gbit IC (yeah I know, I'm dreaming) you would only wire up 32-bits worth of addresses since the CPU can't address the rest of them (since there would be 36-bits worth of addresses, but you can only use 32 of them), but that's a waste of money, so they won't do it.

I'm getting the distinct impression that you've done a Google search and you think you know what you're talking about.

 

[NeoXF]

Mobile devices are different considering you may only have one or two DDR chips (single ICs, not DIMMs) as opposed to at least 8 in one rank on a Computer DIMM. How many memory addresses DRAM and SRAM has depends on the size of the IC. It wouldn't make sense to pin out 32-bits or 64-bits worth of addresses if you're only going to use 28 of them (say for a 256Mbit chip). You would wire up 28 pins and leave the other 4 not connected (assuming one pin for every bit on the address bus.) Same way if you have the opposite problem. If you have a 64Gbit IC (yeah I know, I'm dreaming) you would only wire up 32-bits worth of addresses since the CPU can't address the rest of them (since there would be 36-bits worth of addresses, but you can only use 32 of them), but that's a waste of money, so they won't do it.

I'm getting the distinct impression that you've done a Google search and you think you know what you're talking about.

I'm getting a distinct impression that I don't give a damn about your impressions. What I stated is fact, 32bit ARM SoCs use 32bit LPDDRs, not 64bit like you're implying as the golden standard (and now seem to backtrack on, with fancy technical words for credibility bonus) beyond that, I don't know if 32bits per channel is something system-specific, or 32/64 bit architecture specific, or not, but since it's related to LPDDR, I see it fit to this article, what I don't see fit as much, is desktop memory subjects. End of discussion.

 

[Aquinus]

I'm getting a distinct impression that I don't give a damn about your impressions. What I stated is fact, 32bit ARM SoCs use 32bit LPDDRs, beyond that, I don't know if 32bits per channel is something system-specific, or 32/64 bit architecture specific, or not, but since it's related to LPDDR, I see it fit to this article, end of discussion.

That's because mobile devices like phones don't use a full rank of memory ICs. There is a difference between being related and not knowing what you're talking about. So stop acting immature and do some research.

 

[NeoXF]

That's because mobile devices like phones don't use a full rank of memory ICs. There is a difference between being related and not knowing what you're talking about. So stop acting immature and do some research.

So you're inciting to conflict and I'm the immature one? LOL, nice one.

Edit: And another shady backtrack, you "accuse" me of googling my statements and then you say "do some research". Another "nice one", are you gong for streaks now?