TSMC Delivers First Fully Functional 16FinFET Networking Processor

[btarunr]

TSMC today announced that its collaboration with HiSilicon Technologies Co, Ltd. has successfully produced the foundry segment's first fully functional ARM-based networking processor withFinFET technology. This milestone is a strong testimonial to deep collaboration between the two companies and TSMC's commitment to providing industry-leading technology to meet the increasing customer demand for the next generation of high-performance, energy-efficient devices.

TSMC's 16FinFET process promises impressive speed and power improvements as well as leakage reduction. All of these advantages overcome challenges that have become critical barriers to further scaling of advanced SoC technology. It has twice the gate density of TSMC's 28HPM process, and operates more than 40% faster at the same total power, or reduces total power over 60% at the same speed.

"Our FinFET R&D goes back over a decade and we are pleased to see the tremendous efforts resulted in this achievement," said TSMC President and Co-CEO, Dr. Mark Liu. "We are confident in our abilities to maximize the technology's capabilities and bring results that match our long track record of foundry leadership in advanced technology nodes."

TSMC's 16FinFET has entered risk production with excellent yields after completing all reliability qualifications in November 2013. This paves the way for TSMC and customers to engage in more future product tape-outs, pilot activities and early sampling.

Built on TSMC's 16FinFET process, HiSilicon's new processor enables a significant leap in performance and power optimization supporting high-end networking applications. By leveraging TSMC's production-proven heterogeneous CoWoS (Chip-on-Wafer-on-Substrate) 3D IC packaging process, HiSilicon integrates its 16-nanometer logic chips with a 28-nanometer I/O chip for a cost-effective system solution.

"We are delighted to see TSMC's FinFET technology and CoWoSsolution successfully bringing our innovative designs to working silicon," said HiSilicon President Teresa He."This industry's first 32-core ARM Cortex-A57 processor we developed for next-generation wireless communications and routers is based on the ARMv8 architecture with processing speeds of up to 2.6GHz. This networking processor's performance increases by three fold compared with its previous generation. Such a highly competitive product can support virtualization, SDN and NFV applications for next-generation base stations, routers and other networking equipment, and meet our time-to-market goals."

View at TechPowerUp Main Site

 

[RejZoR]

I'd want a 32 core 2,6 GHz router Processing QoS with nearly zero latency...

 

[Ferrum Master]

Well I can recommend something from my turf..

36cores@1.2Ghz and 16GB RAM...

http://routerboard.com/CCR1036-8G-2SplusEM

 

[redeye]

hello iphone 7... or iPhone 0x edition...iPhone hex edition, iPhone 0xF nm edition...iPhone 16 nm edition. lol

 

[Prima.Vera]

I'd want a 32 core 2,6 GHz router Processing QoS with nearly zero latency...

Cannot beat the speed of light mate.

 

[Hilux SSRG]

"TSMC's 16FinFET has entered risk production"

Does that mean consumers will see actual product releases in 1-2 years? Apple's iphone 6 is on TMSC & Samsung's 20nm now.

 

[redeye]

to quote www.edn.com in an article about risk production at 28nm... (i assume the following applies to 16nm...) but the Original article states that they have CPU designed, so they must be further along that this quote explains...

It’s a chicken-and-egg issue. At the start of risk production, by definition there have been no customer designs put through the fab. Actually this is not quite true, Sun explained. Before the start of risk production the company has already run a number of shuttles with test chips from customers, so foundry and clients are already starting to wring out the more critical structures in the first customer designs. But these test shuttles are not full chips either.

So to convince themselves that the line is ready to take on a wafer full of real chips instead of a wafer full of test structures, TSMC develops an SRAM. As reported in a press release earlier this week, the vehicle for all three announced variants of the 28nm process—low-power with SiON gate stack, G with high-k/metal-gate, and LP with high-k/metal-gate–happens to be a 64Mbit part. TSMC says it now has yield at target performance for the SRAM on all three processes.

Running the SRAM vehicle through the fab is just one step in many, according to Sun. Before the SRAM goes through, and in fact before process freeze, TSMC runs test chips designed to stress each of the mandatory and recommended design rules. Information from these runs goes into the version of the rule deck that goes out with the first PDKs. From there on, work is more or less continuous as the process engineers work out issues, tune the process ever closer to the target performance and yield, and tweak the design rules. At some point in the schedule, the engineers judge the process ready to try full SRAM wafers.

SRAM is not an arbitrary choice. The design includes densely-packed arrays of minimum-dimension features. And because the arrays are addressable and testable, the SRAM makes a good diagnostic pattern as. By simply writing and reading data patterns you can examine not only whether the whole die is working, but the locations of the problems.

"The SRAM vehicle is what we run through evaluation, high-temperature life testing, and the rest of the qualification tests," Sun said. "It certifies that the process is now reliable enough to try running full customer designs." But Sun emphasized that those first design runs—the risk production runs—are done with the full process, not with a subset of the full specs or with an extra-restrictive rule set.

Work will continue after the SRAM runs. Sun said that early customer designs usually have some features that lie outside the design rules, and hence require discussion and perhaps process tweaks. And once customer risk-production wafers are finished, they in their turn will go into the qualification process to be studied and measured. But the SRAM is the major signal that it’s time to start the move to tape-out for the first few designs, send them in, and see what happens.

 

[Steevo]

I'd want a 32 core 2,6 GHz router Processing QoS with nearly zero latency...

Unless you have more than a few hundred network devices and enough down/up bandwidth to fill that stream we are out of need for more network precessing power, we need more internet speeds and to give comcast and other companies a kick in the junk for holding back speeds so the CEO and board can buy another home and jet.