SAMSUNG Develops New, Highly Efficient Stacking Process for DRAM

[malware]

Samsung Electronics, has developed the first all-DRAM stacked memory package using 'through silicon via' (TSV) technology, which will soon result in memory packages that are faster, smaller and consume less power. The new wafer-level-processed stacked package (WSP) consists of four 512 megabit DDR2 DRAM chips that offer a combined 2 gigabits (Gb) of high density memory. Using the TSV-processed 2Gb DRAMs, Samsung can create a 4GB DIMM based on advanced WSP technology for the first time. Samsung's proprietary WSP technology not only reduces the overall package size, but also permits the chips to operate faster and use less power.




"The innovative TSV-based MCP (multi-chip package) stacking technology offers next-generation packaging solution that will accommodate the ever-growing demand for smaller-sized, high-speed, high-density memory," said Tae-Gyeong Chung, vice president, Interconnect Technology Development Team, Memory Division, Samsung Electronics. "In addition, the performance advancements achieved by our WSP technology can be utilized in many diverse combinations of semiconductor packaging, such as system-in-package solutions that combine logic with memory.

In today's MCPs, memory chips are connected by wire bonding, requiring vertical spacing between dies that is tens of microns deep. That wire bonding process also requires horizontal spacing on the package board hundreds of microns wide for the die-connecting wires. By contrast, Samsung's WSP technology forms laser-cut micron-sized holes that penetrate the silicon vertically to connect the memory circuits directly with a copper (Cu) filling, eliminating the need for gaps of extra space and wires protruding beyond the sides of the dies. These advantages permit Samsung's WSP to offer a significantly smaller footprint and thinner package.

Inside the new WSP, the TSV is housed within an aluminum (Al) pad to escape the performance-slow-down effect caused by the redistribution layer. Due to the complexity of DRAM stacking, this represented a much more difficult engineering feat than that accomplished with the first WSP, announced last year involving NAND flash dies.

There has been considerable concern that MCPs with high-speed memory chips with speed of 1.6Gb/ps next generation DRAM, would suffer from performance limitations when connected using current technologies. Samsung's WSP technology resolves these concerns.

In addition, as the back side of the wafer is ground away to make a thinner stack of multiple dies, the wafer has had a tendency to curve, creating physical distortion in the die. To overcome this additional critical concern in designing low-profile, high-density MCPs containing DRAM circuitry, Samsung's proprietary wafer-thinning technology, announced last year, has been applied to improve the thin-die-cutting process.

Advanced package solutions are increasingly important requirements for enabling high-speed, high-density memory solutions. Samsung's new stacked package design supports the rapid industry demand for high density, high performance semiconductor solutions that will support next-generation computing systems in 2010 and beyond.

View at TechPowerUp Main Site

 

[Wile E]

I wonder what this means for the finished product in terms of capacity, latencies, and power consumption. They mentioned 4GB modules, but at what voltage and latencies? I also wonder if this intended for DDR2 or DDR3?

 

[kakazza]

I wonder what this means for the finished product in terms of capacity, latencies, and power consumption. They mentioned 4GB modules, but at what voltage and latencies? I also wonder if this intended for DDR2 or DDR3?

Clicking source link is HARD!

The new wafer-level-processed stacked package (WSP) consists of four 512 megabit (Mb) DDR2 (second generation, double data rate) DRAM (dynamic random access memory) chips that offer a combined 2 gigabits (Gb) of high density memory.

But I doubt they'll say "naw, this is for DDR2 only, DDR3 won't get it".

 

[WeStSiDePLaYa]

definetly wont be good at overclocking.


With that many IC's the chances of a single bad IC lowering the speed of the entire stick is high.

Also, this would make binning more difficult as well, as the bundled ICs cant be seperated for binning.


DDR1 IC piggybacking was a better method IMO.

 

[WarEagleAU]

Actually, I believe this will make oc'ing alot better as well as lower power requirements, probably lower latencies and higher speeds. The fact there there is less gappage and direct connection with the copper and not the pcb leads, is more efficient. Im sure this will be for DDR2-3-4 and probably 5. Nice going Samsung.

 

[WeStSiDePLaYa]

Actually, I believe this will make oc'ing alot better as well as lower power requirements, probably lower latencies and higher speeds. The fact there there is less gappage and direct connection with the copper and not the pcb leads, is more efficient. Im sure this will be for DDR2-3-4 and probably 5. Nice going Samsung.

then you obviously arent understanding this technology.

This is IC stacking. Plan and simple. it has never led to increased speeds, or lowered latencies.

Also, you must not understand binning, as this will make binning more less effecient, as the yield of above spec chips will be less, due to 4 chips being stacked together.

Stacking is the short-cut way of getting higher density IC's. And there is a reason stacked dimms are unpopular, and uncommon.



Because now instead instead of 16 IC's on a normal double sided stick, you have 64 IC's on a double sided stick, in 16 packages.

So if even ONE of those 64 IC's doesnt clock well, it holds back the WHOLE stick.

And now with binning, instead of only needing to find a good IC in one package. they have to find one package with 4 good IC's.


Overclocking is really a odds game, and the lower the number the IC's on a single component the better the odds that there is no bunk ones.

 

[Mussels]

its upto OCZ and corsair to make it Overclock

 

[Wile E]

Clicking source link is HARD!



But I doubt they'll say "naw, this is for DDR2 only, DDR3 won't get it".

So I missed the DDR2 comment, but I still didn't see anything in reference to latencies and power consumption estimates.

 

[Mussels]

well of course, this is about a new technique, not about a stick of ram itself.

Latency and power depend on the modules and voltages used, which comes in later.

 

[Wile E]

well of course, this is about a new technique, not about a stick of ram itself.

Latency and power depend on the modules and voltages used, which comes in later.

Right, if you read my first post, I was just wondering what this will mean for the final product. I was just hoping for some estimates.

 

[Mussels]

yeah, i know. but estimates.. hell, look at DDR - 2.5V for the spec, and people ran upto 3.3V (stock!) on some modules - whatever they say, some ram company is going to make it different.