AMD Confirms Key "Summit Ridge" Specs

[Casecutter]

and then there is 2160P when the 390/x destroy the 970/980

It hardly mattered as those weren't a appropriate purchases for entry 4K, except with a game or two.

 

[cdawall]

It hardly mattered as those weren't a appropriate purchases for entry 4K, except with a game or two.

I have played 4K without issues on a single 390, the vast majority of games comfortably play at >40FPS at 4K and medium/high settings. Turns out you can actually enjoy games without setting everything to max.

 

[TheGuruStud]

I have played 4K without issues on a single 390, the vast majority of games comfortably play at >40FPS at 4K and medium/high settings. Turns out you can actually enjoy games without setting everything to max.

Heresy! Heathen! Sodomite!

Dirty Console Peasant!

 

[cdawall]

Heresy! Heathen! Sodomite!

Dirty Console Peasant!

Hey now I didn't say medium settings at 720P/1080P

 

[PP Mguire]

I have played 4K without issues on a single 390, the vast majority of games comfortably play at >40FPS at 4K and medium/high settings. Turns out you can actually enjoy games without setting everything to max.

Whoa whoa speak for yourself buddy

 

[BiggieShady]

Turns out you can actually enjoy games without setting everything to max.

It goes something like this: I'll put it to max just to see how it looks, *drool* damn dat eye candy looks nice, *random religious curse* which damn setting tanks the frame rate this much, and after that there goes an hour of your life spent messing with the display options.

 

[chuck216]

Hey now I didn't say medium settings at 720P/1080P

I'm perfectly happy with my R9 390 at max settings and 1440p

 

[Pill Monster]

Who knows what he meant, but you're wrong, same instruction set, different micro architectures (and architectures both) cpus can have their instructions per clock count (IPC) compared.
Name says it all, how many x86/x64 instructions by average can a single core execute in a single clock tick (you do that measurement actually on a gazillion clock ticks then divide result with gazillion).
You gotta remember these are super scalar processors and single core is capable of issuing multiple less wide instructions simultaneously and some instructions read from different cache levels with different latencies, some from memory, some just process the instruction operands ... so scheduler has to calculate dependency and arrange mutually non-dependent short running and long running instructions of different instruction widths to execute in parallel (on that single core) in a way that at any given time maximum possible usage of all units is achieved (for example, doing several ALU instructions on cache while waiting on fetch from a memory controller).
You have a myriad of different algorithms there so every little optimization in cache, memory controller, branch prediction, pipeline depth reduction will certainly affect IPC. The whole architecture including the micro architecture.

Well said.