I highly doubt XPoint is DDR4 compatible because of the massive performance drop when the CPU tries to access it. Most likely, select Xeon processors will have DIMMs + XPoint DIMMs with two separate controllers (one for each) and only be compatible with a land grid array that has DIMM slots for both.
That's another thing. You're already talking about some optimization. And you're right: the memory controller has to know, what kind of DIMM is plugged in.
Furthermore, RAM needs to be refreshed from time to time (there's an instructions for that) - XPoint doesn't. But once the MC knows what tech is on the DIMM, it'll know what instructions to send.
But other than that, it's accessed the same way RAM is, so it could use the same instructions set (~subset).
So how does the system know how to use it if it sees it as just another DIMM stick? There have to be some changes under the hood.
The system "knows" because it's been designed to know. It also knows the clocks and latencies of RAM.
That's why Optane is only supported by some CPU+chipset combinations.
But other than that Optane is a lot like RAM and, no offense, all these discussions about it being a cache of some sort are pointless.
It's not like the whole PC idea has to be rebuilt because we're forcing an SSD into a RAM socket. XPoint is a lot more similar to RAM than to a NAND SSD. We should treat it that way.
So now we simply have 2 types of DIMM: fast DDR and slow (but larger and persistent) XPoint. It's only important for the PC to know how to use them.
If we had such choice from the start, XPoint would seem totally natural.