PCI-SIG Fast Tracks Evolution to 32 GT/s with PCI Express 5.0 Architecture

[btarunr]

PCI-SIG Developers Conference 2017 - PCI-SIG, the organization responsible for the widely adopted PCI Express (PCIe) industry-standard input/output (I/O) technology, today announced 32GT/s as the next progression in speed for the PCIe 5.0 architecture, targeting high-performance applications such as artificial intelligence, machine learning, gaming, visual computing, storage and networking. Slated for completion in 2019, the specification development is well underway with Revision 0.3 already available to PCI-SIG member companies.

"In our 25-year history, PCI-SIG has maintained its commitment to our rigorous specification development process, while delivering specifications that are in lock-step with industry requirements for high-performance I/O," said Al Yanes, PCI-SIG Chairman and President. "PCIe 5.0 technology is the next evolution that will set the standard for speed, and we are confident that its 32GT/s bandwidth will surpass industry needs."

The preceding PCIe 4.0 specification is designed with key functional enhancements that future-proof the PCIe architecture design, thereby accelerating future specification development. This undertaking, along with improved silicon design processes, serves as the foundation for the PCIe 5.0 specification.

For high-end networking like 400Gb Ethernet solutions and dual 200Gb/s InfiniBand, the PCIe 5.0 architecture operates at full duplex and provides up to 128GB/s in bandwidth. The higher bandwidth will serve accelerator and GPU attachments, as well as constricted form factor applications needing to increase channel width.

"With the onset of Big Data, high-performance applications and the arrival of next generation non-volatile memories, storage devices have a voracious appetite for increasing performance," said Amber Huffman, President of NVM Express, Inc. "We are pleased to see the PCI-SIG continue to evolve this interface technology to enable NVMe SSDs for the enterprise and data center to leverage the scalability of the PCIe architecture, both in higher bandwidth and lower latency."

View at TechPowerUp Main Site

 

[R0H1T]

& yet here we are still waiting for PCIe 4.0

 

[Prima.Vera]

For high-end networking like 400Gb Ethernet solutions and dual 200Gb/s InfiniBand, the PCIe 5.0 architecture operates at full duplex and provides up to 128GB/s in bandwidth.

Sorry, I am confused. 128GB/s = 1Tbps speed, not 400Gbps... or am I missing something?
Anyways 400Gb Ethernet?? We don't even have 10Gb Ethernet as mainstream, except for fiber ports on datacenter switches, but 400Gb??

 

[fynxer]

This is really getting ridiculous, it cannot take up to 8 years to release a new Pcie standard like with Pcie 4.0.

There must be other forces with unknown motives behind this delay than just technical issues.

Read this from TechRepublic.com about Intel dragging their feet with Pcie 4.0

"Delays in computer industry standards are not normally a big deal. It's common knowledge that such things take time to get right, but almost all major hardware companies except Intel are starting to work together on alternate plans. Such companies already use and support PCIe 3.0 and 3.1, but the information world is moving too fast to wait much longer, they argue. There is also a business motivation: Intel's recent purchases of smaller companies in the hardware acceleration and programmable chip niches are leaving other hardware giants without a choice."

http://www.techrepublic.com/article/new-pci-express-4-0-delay-may-empower-next-gen-alternatives/

Intel is known to use it's dominating position in the PC space to drag out on tech evolution with the purpose to further line their pockets with money no matter what the cost to others.

 

[Prima.Vera]

This is really getting ridiculous, it cannot take up to 8 years to release a new Pcie standard like with Pcie 4.0.
There must be other forces with unknown motives behind this delay than just technical issues.

Common man. Think about it a little. PCIe 4.0 will double the speeds of PCIe3.0. Meaning 8 lines PCIe4.0 will be equivalent of 16 lines PCIe3.0
Now the new HEDT CPUs from Intel how many PCIe lines they have??

 

[Xajel]

This is really getting ridiculous, it cannot take up to 8 years to release a new Pcie standard like with Pcie 4.0.

There must be other forces with unknown motives behind this delay than just technical issues.

Read this from TechRepublic.com about Intel dragging their feet with Pcie 4.0

"Delays in computer industry standards are not normally a big deal. It's common knowledge that such things take time to get right, but almost all major hardware companies except Intel are starting to work together on alternate plans. Such companies already use and support PCIe 3.0 and 3.1, but the information world is moving too fast to wait much longer, they argue. There is also a business motivation: Intel's recent purchases of smaller companies in the hardware acceleration and programmable chip niches are leaving other hardware giants without a choice."

http://www.techrepublic.com/article/new-pci-express-4-0-delay-may-empower-next-gen-alternatives/

Intel is known to use it's dominating position in the PC space to drag out on tech evolution with the purpose to further line their pockets with money no matter what the cost to others.

When they announced PCIe 4.0 back in 2011, it was just plans and design target.. the specifications is not finalised yet, last year it had it's first demonstration, and it said to be finalised by the end of 2016, but it got delayed again. the new finalisation timeframe is this year 2017...

Next gen of GPU's ( planned for 2018 ) are planned to be the first wave of PCIe 4.0 products, and platforms ( eg. CPU's, Chipsets & Motherboards ) will need more time as it will require a new sockets also... AMD said they won't change the AM4 socket till PCIe 4.0 and DDR5 comes.. but if DDR5 will come very late then we might see AM4+ with PCIe 4.0...

 

[Nokiron]

Sorry, I am confused. 128GB/s = 1Tbps speed, not 400Gbps... or am I missing something?
Anyways 400Gb Ethernet?? We don't even have 10Gb Ethernet as mainstream, except for fiber ports on datacenter switches, but 400Gb??

I believe the current roadmap for IEEE tops out at 400Gbps (P802.3bs).

 

[Hood]

This is good news, because even the announcement of 5.0 should accelerate the move to 4.0 - which doubles the bandwidth from 3.0, and requires intense cooperation among all interested parties to ensure compatibility, plus endless hours of validation and certification for each vendor. Not surprising that it's taking a while, but we'll get there sooner or later.

 

[Gasaraki]

Sorry, I am confused. 128GB/s = 1Tbps speed, not 400Gbps... or am I missing something?
Anyways 400Gb Ethernet?? We don't even have 10Gb Ethernet as mainstream, except for fiber ports on datacenter switches, but 400Gb??

The PCIe bus is not just there to provide the 400Gb Ethernet. It needs to do other things. The bus itself is going to operate at 128GB/s in order to support 400Gb Ethernet, M2, GPU, etc.

 

[Caring1]

No increase in available power through the slot mentioned in the standards?

 

[The Von Matrices]

And users will still complain that their PCIe 5.0 GPU is losing 0.01 FPS because it is only getting 32GB/s of bandwidth at PCIe 5.0 x8 instead of x16.

The PCIe bus is not just there to provide the 400Gb Ethernet. It needs to do other things. The bus itself is going to operate at 128GB/s in order to support 400Gb Ethernet, M2, GPU, etc.

BTW, the standard runs at 32GT/s, which means 4GB/s/lane. So that 128 GB/s bandwidth is for the mythical x32 connection that we have yet to see. That said, 400 Gb/s is pushing the limits of PCIe 5.0. A PCIe 5.0 x16 slot is just wide enough at 640 Gb/s while a PCIe 5.0 x8 slot would be a bottleneck at 320 Gb/s.

 

[Prima.Vera]

Yeah, but 400Gbps Ethernet??? Never heard of it.

 

[AnarchoPrimitiv]

& yet here we are still waiting for PCIe 4.0

PCI-SIG has no control over industry adoption, and just like pretty much every other standard (HDMI, DP, etc) the newest revision is always at least a full year ahead of downstream industry adoption and implementation.