AMD 400-series Chipset Surfaces on PCI-SIG, PCIe 3.0 General Purpose Confirmed

[notb]

With that said, it's my general belief that chipsets should be capable of reasonably handling all of a boards I/O needs aside from PCIe. PCIe should be there but, it's a convenience thing, not a performance thing, given bandwidth and latency but, if people expect full performance out of NVMe RAID, then the PCH (in my opinion,) shouldn't be the option because anything that demands high performance and low latency should be wired directly to the CPU.

But then again... PC I/O have changed a lot lately, haven't they?
Not so long ago we had fast internal interfaces (PCI, SATA) and slow external ones (USB). It's not true anymore. Where do you think Thunderbolt 3 should be wired to? Keep in mind it may be used for external GPU or majority of PC storage (even the "operational" kind, not some seldom used backups). Notebooks drive the PC evolution and desktops will have to accept some technologies and design decisions.

 

[Aquinus]

Not so long ago we had fast internal interfaces (PCI, SATA) and slow external ones (USB). It's not true anymore. Where do you think Thunderbolt 3 should be wired to? Keep in mind it may be used for external GPU or majority of PC storage (even the "operational" kind, not some seldom used backups). Notebooks drive the PC evolution and desktops will have to accept some technologies and design decisions.

It's hard to say because you don't know a lot about what's on the other end of the TB cable. It could be a display, it could be a GPU, it could be a network adapter. What you also don't know is the length of the cable or the latency introduced by the cable and the hardware it houses. Don't forget that the signal coming out of a TB port is not the same signal getting sent over the wire (or fiber) itself. That's why optical TB cables can exist, which introduces the problem of latency. Signals don't travel faster than the speed of light and assuming you actually get the speed of light (forget the time it takes to convert the signal to and from the signal from the port,) you introduce 1 nanosecond of latency for every ~0.3m of cable (assuming straight line, which twisted pairs aren't but, fiber is.) So If the cable is a 3 meter long optical cable, you've already introduced 10 nanoseconds of latency by the cable alone and will add another 10ns for every additional 3 meters on top of the constant latency introduced by the conversion circuitry.

So, TB is already a terrible choice for latency. If the PCH had the bandwidth, adding a little more probably wouldn't kill it however, you might want it connected to the CPU for the very reason that you're already dealing with a lot of latency because of how it works. So, there are trade-offs whatever way you go. I think that GPUs over TB is the exception, not the rule so, I would probably say, not the CPU if CPU PCIe lanes are at a premium. The cost of having it go through the PCH is probably not very high though because latency sensitive applications will already be suffering over TB compared to being in an actual PCIe slot.

 

[TheLostSwede]

Seriously, too many people in this thread are getting things out of this news post that makes no sense.

Look at that, Intel's chipsets apparently only supports four PCIe slots as well if I read this like some of you do...
That's not what it says though, it says that the maximum lane width is a total of four lanes, i.e. the chipsets can ad the most provide a x4 slot, i.e. for an M.2 NVMe slot for example...

This doesn't say anything about how many lanes the chipsets provide, at all.

I think you all need to take a chill pill and read things before posting angry comments about things you don't fully understand.

 

[Aquinus]

Seriously, too many people in this thread are getting things out of this news post that makes no sense.

Look at that, Intel's chipsets apparently only supports four PCIe slots as well if I read this like some of you do...
That's not what it says though, it says that the maximum lane width is a total of four lanes, i.e. the chipsets can ad the most provide a x4 slot, i.e. for an M.2 NVMe slot for example...

This doesn't say anything about how many lanes the chipsets provide, at all.

View attachment 95259

I think you all need to take a chill pill and read things before posting angry comments about things you don't fully understand.

No, it says that it's replacing the 300-series chipset which only has 8 PCIe 2.0 lanes and that the entire article revolves around the addition of PCIe 3.0 to the chipset. With no further information, I would expect there to be just as many PCIe lanes as in the past, just running at PCIe 3.0 instead, which means no more than two, full, 4x slots or 8 PCIe lanes (just like it's predecessor.)

 

[notb]

Look at that, Intel's chipsets apparently only supports four PCIe slots as well if I read this like some of you do...

So the recommended approach would be: stop looking at those tables, thinking about PCIe lanes and all that technical stuff.
Simple fact is: Z370 motherboards offer up to three M.2 x4 slots (or two M.2 and Thunderbolt 3). X370 variants (even put in the same segment - like AsRock Taichi) offer a single M.2 x4.

 

[Imsochobo]

So the recommended approach would be: stop looking at those tables, thinking about PCIe lanes and all that technical stuff.
Simple fact is: Z370 motherboards offer up to three M.2 x4 slots (or two M.2 and Thunderbolt 3). X370 variants (even put in the same segment - like AsRock Taichi) offer a single M.2 x4.

They do, but use One 960 pro and the others cannot be used pretty much, throw in a usb3 device and half of the nvme can be used up.

Question is:
What the hell is the point ?, it offers no performance, it increases the latency and decreases performance thus it's pointless you might aswell have NVME to SATA at this point.
Intel says up to 24x pci-e through chipset or something while it's limited by 4X to the rest of the system so I wonder... what is the point of it all? sharing 4x on 2 drives is ok, but 3 drives, usb, sound, network, sata+++ then you start getting into a serious x4 bottleneck >_<

AMD's approach is easier: everything has almost dedicated bandwidth.

Not that I'd want to see two cool fancy 4X on the boards but in theory if ryzen 2 comes with PCI-E 4.0 the existing nvme and pci-e slots should be pci-e 4 on 300 series boards but not to chipset, free upgrade on older chipsets too.
Thus making gpu and other pci-e slots also pci-e 4.0 for those not through chipset.

Hopefully that is what happens