Rambus Inc. today announced the GDDR6 (Graphics Double Data Rate) Memory PHY IP Core targeted for high-performance applications including cryptocurrency mining, artificial intelligence (AI), ADAS (advanced driver assistance systems) and networking. Leveraging almost 30 years of high-speed interface design expertise and using advanced leading-edge FinFET process nodes, the Rambus GDDR6 PHY architecture will provide the industry's highest speed of up to 16 Gbps, while utilizing established packaging and testing techniques.
"The high bandwidth delivered by GDDR6 makes it uniquely qualified to perform data-intensive applications such as HPC (high performance computing), AI, autonomous vehicles, and high-speed networking," said Luc Seraphin, SVP and general manager of the Rambus Memory and Interfaces Division. "We are excited to be the first IP provider to offer a GDDR6 PHY solution with industry-leading performance designed with power efficiency and high signal margins for these applications."
Rambus GDDR6 Memory PHY Technical Highlights:
Demonstration Details at DesignCon 2018
At DesignCon from Jan. 31 - Feb. 1, 2018 in Santa Clara, California, Rambus will demonstrate a memory channel signaling at GDDR6 speeds. Rambus will also present, "High-speed memory architectures for next-generation applications," starting at 3:45 pm PT on Jan. 31 in the room, "Great America 3," that will discuss GDDR6 as well as other leading technologies. Visit Rambus at Booth 627 to learn more about GDDR6 applications.
For more information on Rambus GDDR6 technology, please visit https://www.rambus.com/gddr6.
View at TechPowerUp Main Site
"The high bandwidth delivered by GDDR6 makes it uniquely qualified to perform data-intensive applications such as HPC (high performance computing), AI, autonomous vehicles, and high-speed networking," said Luc Seraphin, SVP and general manager of the Rambus Memory and Interfaces Division. "We are excited to be the first IP provider to offer a GDDR6 PHY solution with industry-leading performance designed with power efficiency and high signal margins for these applications."
Rambus GDDR6 Memory PHY Technical Highlights:
- Standards compliant
- Flexible delivery of IP core: works with ASIC/SoC layout requirements
- Speed bins: 12 Gbps, 14 Gbps, 16 Gbps
- 2 x 16 bit Channels, for a maximum bandwidth of 512 Gbps
Demonstration Details at DesignCon 2018
At DesignCon from Jan. 31 - Feb. 1, 2018 in Santa Clara, California, Rambus will demonstrate a memory channel signaling at GDDR6 speeds. Rambus will also present, "High-speed memory architectures for next-generation applications," starting at 3:45 pm PT on Jan. 31 in the room, "Great America 3," that will discuss GDDR6 as well as other leading technologies. Visit Rambus at Booth 627 to learn more about GDDR6 applications.
For more information on Rambus GDDR6 technology, please visit https://www.rambus.com/gddr6.
View at TechPowerUp Main Site
