ASMedia Readies ASM2824 PCIe Switch Anticipating a Rise in M.2 Slots

[btarunr]

ASMedia is giving finishing touches to the ASM2824 PCI-Express gen 3.0 x24 switch. With half the fabric as the PLX PEX8747, the chip takes in PCI-Express 3.0 x8, and puts out four PCI-Express 3.0 x4 connections. In theory, this would let a motherboard designer create four M.2 PCIe 3.0 x4 slots from 8 downstream PCIe lanes of the Intel Z390 chipset, saving the remaining PCIe lanes for onboard USB 3.1 controllers (preferably sourced from ASMedia itself), since Intel canned the older 14 nm version of the Z390, which was supposed to put out six 10 Gbps USB 3.1 gen 2 and ten 5 Gbps USB 3.1 gen 1 ports directly from the PCH.

With all four downstream slots populated, ASMedia promises NVMe RAID bandwidths of up to 6,500 MB/s, with some CDM numbers even crossing 6,700 MB/s. Then again, one has to take into account that the test platform probably had the ASM2824 wired to the CPU's PCIe root-complex, and not that of the chipset. Intel is yet to modernize the lousy DMI 3.0 chipset-bus between its latest processors and chipset, and is physically PCI-Express 3.0 x4, which is fundamentally outdated for the bandwidth-heavy interfaces of this generation, such as USB 3.1, M.2 NVMe, and even the upcoming SD Express. The ASM2824 is also a godsend for the AMD AM4 platform, which not only has the same PCI-Express 3.0 x4 chipset bus between the AM4 SoC and the X470 chipset, but also a poor downstream PCIe feature-set of the X470, with just 8 gen 2.0 lanes. Motherboard designers can wire out all of those lanes to an ASM2824 for up to 24 downstream lanes.



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[bug]

Ok, this question has been bugging me for a while and I haven't found an answer (without reading tech specs of the implementation, which I'm not sure are freely available). When two PCIe devices connected to the southbridge talk to each other, is the data stream handled locally by the southbridge? Or does it still have to go all the way to the CPU root complex?

 

[btarunr]

Ok, this question has been bugging me for a while and I haven't found an answer (without reading tech specs of the implementation, which I'm not sure are freely available). When two PCIe devices connected to the southbridge talk to each other, is the data stream handled locally by the southbridge? Or does it still have to go all the way to the CPU root complex?

It goes to the CPU because the CPU still does all of the HSP (host signal processing). Let's say you're downloading something:

• The CPU has to first process the network stack because your GbE PHY does buggerall other than converting analog waveforms into ones and zeroes (the CPU turns those ones and zeroes into meaningful data).
• The CPU then has to process the storage stack AHCI/NVMe to write your download to disk, because the chipset-integrated SATA controllers do buggerall other than converting a stream of ones and zeroes into the SATA physical layer waveform (unlike real RAID HBAs that can process their own stacks).

Basically any chipset-attached device in your computer that relies on the CPU to do the heavy lifting, will have to send raw data through the chipset bus to the CPU. It's a damn travesty.

 

[bug]

It goes to the CPU because the CPU still does all of the HSP (host signal processing). Let's say you're downloading something:

• The CPU has to first process the network stack because your GbE PHY does buggerall other than converting analog waveforms into ones and zeroes (the CPU turns those ones and zeroes into meaningful data).
• The CPU then has to process the storage stack AHCI/NVMe to write your download to disk, because the chipset-integrated SATA controllers do buggerall unlike real RAID HBAs that can process their own stacks.

Basically any chipset-attached device in your computer that relies on the CPU to do the heavy lifting, will have to send raw data through the chipset bus to the CPU. It's a damn travesty.

I wasn't thinking about downloading, but rather moving data from one device to the other. And hoping it could be handled locally. Sadly, you say it isn't

 

[btarunr]

I wasn't thinking about downloading, but rather moving data from one device to the other. And hoping it could be handled locally. Sadly, you say it isn't

I was describing the same (moving data from your network controller to your SATA controller (two things that are chipset-attached)).

 

[bug]

I was describing the same (moving data from your network controller to your SATA controller (two things that are chipset-attached)).

Right. I read that in a hurry and it went right over my head.
Long story short, it's not the lack of a bazillion cores that's going to kill us (i.e. hold system performance back), but the lack of PCIe lanes.

 

[nemesis.ie]

Right. I read that in a hurry and it went right over my head.
Long story short, it's not the lack of a bazillion cores that's going to kill us (i.e. hold system performance back), but the lack of PCIe lanes.

A good thing that a certain company is starting to give us both.

(TR I am looking at you, but you need to sort out your chipset connect or ditch it, too)

 

[iO]

Well, AMDs Z490 was exactly that, a PEX chip to add some PCIe lanes to the X470 chipset. Which got canceled because of the additional cost, so don't hold your breath...

 

[bug]

A good thing that a certain company is starting to give us both.

(TR I am looking at you, but you need to sort out your chipset connect or ditch it, too)

Yeah, because everybody wants to spend $500+ on a CPU. A few cornercases aside, TR is a terrible pick for a home desktop.
Edit: i love it as an engineering achievement, tho.

 

[Beerbam]

Right. I read that in a hurry and it went right over my head.
Long story short, it's not the lack of a bazillion cores that's going to kill us (i.e. hold system performance back), but the lack of PCIe lanes.

All PCI Express devices could talk to each other without the CPU involved, you still need a PCI Express switch to connect them.
Even Gen1 was already capable for that.

There is just the little Problem that those devices need the ability to be able to talk to each other and in most cases you need specific OS Drivers.
With professional Graphics Cards it's common standard and you also get the OS drivers.*
There shouldn't be a problem to include that feature between two storage media, and likely already exists, but as always they want more money for additional features.

*I speak of Pro GPU's with additional Pro Features, not just common graphics cards just for the case some mining nerds read that

 

[nemesis.ie]

Yeah, because everybody wants to spend $500+ on a CPU. A few cornercases aside, TR is a terrible pick for a home desktop.
Edit: i love it as an engineering achievement, tho.

Well that's kind of where my comment was heading - you can of course by a TR4 8 core chip, for around the same price as a Ryzen 7 (or I suspect you will when TR 2 is launched).

So at that point it's the platform cost, we have seen some small M-ATX and maybe an ITX TR board, so the real question is, how cheaply could a TR4 style platform be built to be "one chip to rule them all" and replace AM4 for example?

We could also potentially see AM5 with something half-way between AM4 and TR4, i.e. it could take 2 x Zen dice rather than one or 4 ....

So, food for thought/potential direction rather than suggesting TR4 is a suitable option for home use, it is however an option, versus no option.

 

[Gasaraki]

Ok, this question has been bugging me for a while and I haven't found an answer (without reading tech specs of the implementation, which I'm not sure are freely available). When two PCIe devices connected to the southbridge talk to each other, is the data stream handled locally by the southbridge? Or does it still have to go all the way to the CPU root complex?

There are no more southbridges in modern chipsets. Data has to go to the cpu to get processed.

 

[bug]

There are no more southbridges in modern chipsets. Data has to go to the cpu to get processed.

I should have said "the chip formerly known as southbridge" May he rest in peace.

 

[Tomorrow]

Well, AMDs Z490 was exactly that, a PEX chip to add some PCIe lanes to the X470 chipset. Which got canceled because of the additional cost, so don't hold your breath...

Well we can hope that for X570.