AMD Unveils "Zen 2" CPU Architecture and 7 nm Vega Radeon Instinct MI60 at New Horizon

[Tomorrow]

Except nothing that will carry over to Ryzen has been announced. Because I highly doubt we'll get 8 channel RAM on consumer parts. It's AMD's show, I'm not faulting them. I was just saying, I had other expectations.

Edit: I also don't see anything about Zen2 availability in the server space, so good luck with that "Q1 or Q2 2019" prediction.

This was announced and was always planned as enterprise event. I don't know what non-server announcements did you expect from them here? This happens pretty much every time when there's an enterprise event - some people just don't get it.

Mainstream stuff will be discussed at CES keynote at the beginning of January next year. Judging by the data we have now it looks like we might get 16c/32t mainstream part on AM4. That is two chiplets and a controller chip between them. Coupled with improved IPC and clockspeeds things looks pretty good imo.

 

[efikkan]

But thankfully memory always give IPC and that'll be on Zen3 (DDR5).

How does increased memory bandwidth help IPC? (hint: it doesn't)

DDR4 supports up to 3200 MHz, Zen+ up to 2933 MHz and Intel up to 2666 MHz, all JEDEC 1.2V. But I haven't yet found any DIMMs supporting beyond 2666 MHz at 1.2V JEDEC spec.

DDR5 at 1.1V(?) is probably still far away.

 

[Tomorrow]

How does increased memory bandwidth help IPC? (hint: it doesn't)

DDR4 supports up to 3200 MHz, Zen+ up to 2933 MHz and Intel up to 2666 MHz, all JEDEC 1.2V. But I haven't yet found any DIMMs supporting beyond 2666 MHz at 1.2V JEDEC spec.

DDR5 at 1.1V(?) is probably still far away.

IPC is not a fixed number. IPC increases if user uses faster memory, overclocks etc. Looking at single threaded benchmarks the same CPU can have score that varies 20% in either direction.

 

[efikkan]

IPC is not a fixed number. IPC increases if user uses faster memory, overclocks etc. Looking at single threaded benchmarks the same CPU can have score that varies 20% in either direction.

IPC doesn't improve with memory bandwidth, and overclocking memory doesn't impact latency.
AMD do have some impact with their Infinity fabric tied to the memory speed, but memory speed itself doesn't impact IPC.

 

[Imsochobo]

How does increased memory bandwidth help IPC? (hint: it doesn't)

DDR4 supports up to 3200 MHz, Zen+ up to 2933 MHz and Intel up to 2666 MHz, all JEDEC 1.2V. But I haven't yet found any DIMMs supporting beyond 2666 MHz at 1.2V JEDEC spec.

DDR5 at 1.1V(?) is probably still far away.

If we increase memory frequency we can feed the cpu more thus improving performance which equals increase in IPC just like Zen+ L2? cache latency was reduced to 12 cycles from 17 cycles which improved IPC.
Or the old pentiums getting vastly better performance by utilizing cache vs no cache previously ( this is the biggest example of feeding a cpu data = more ipc, cause it was so appearant at the time)
DDR4 memory is just L4 cache for a cpu, some tasks will see no improvements as long as the entire work can fit inside IE L1 cache
A bit simplified but should tell the story


As for 3200mhz kits on 1.2 v
https://www.gskill.com/en/product/f4-3200c16d-16gtzr
https://www.kingston.com/dataSheets/HX432C18FBK2_32.pdf

 

[efikkan]

If we increase memory frequency we can feed the cpu more thus improving performance which equals increase in IPC just like Zen+ L2? cache latency was reduced to 12 cycles from 17 cycles which improved IPC.

Increasing memory bandwidth doesn't decrease memory latency, and doesn't impact cache.

As for 3200mhz kits on 1.2 v

https://www.gskill.com/en/product/f4-3200c16d-16gtzr

It clearly says 3200 MHz at 1.35 V, SPD speed 2133 MHz at 1.2 V.

https://www.kingston.com/dataSheets/HX432C18FBK2_32.pdf

This one seems more promising, I don't see this in the standard JEDEC configurations, but there may be more recent additions than the list in Wikipedia.

 

[Vya Domus]

Didn't thought I would see a day when AMD would outclass Intel in terms of innovation on just about every front. Very impressed.

If we increase memory frequency we can feed the cpu more thus improving performance which equals increase in IPC just like Zen+ L2? cache latency was reduced to 12 cycles from 17 cycles which improved IPC.

Well, there are tow metrics here. An "absolute" ideal IPC value when there are no bottlenecks in the system and a real IPC metric which can indeed be improved by higher memory bandwidth.

 

[Xzibit]

AMD Preview single Epyc Rome (Air cooled, non-Overclock) vs dual socket Intel 8180M

 

[RH92]

Rumors say Intel won't be using HT on Cascadelake for TDP reasons so we are potentially looking at a 48/48 vs 64/128 battle . This will be a slaughter !

 

[moproblems99]

IPC is not a fixed number. IPC increases if user uses faster memory, overclocks etc. Looking at single threaded benchmarks the same CPU can have score that varies 20% in either direction.

Correct me if I am wrong, but isn't IPC = instructions per cycle. Memory bandwidth and overclocking are not going to affect ipc. I suppose memory bandwidth could if the processor was ridiculously starved by the memory pipeline but I doubt any modern processors are. Overclocking is not going to increase IPC but rather it is going to increase the number of cycles...thus allowing you to do more in the same time.

 

[krykry]

Correct me if I am wrong, but isn't IPC = instructions per cycle. Memory bandwidth and overclocking are not going to affect ipc. I suppose memory bandwidth could if the processor was ridiculously starved by the memory pipeline but I doubt any modern processors are. Overclocking is not going to increase IPC but rather it is going to increase the number of cycles...thus allowing you to do more in the same time.

People at some point started confusing IPC with single core performance. IPC is a statistic describing the amount of operations the CPU core can do at one cycle.
Although IPC does affect single core performance, it does not describe the final performance which is also affected by delays, timing, bandwidth and so on.

 

[chaosmassive]

Idk, I'm rather disappointed. This wasn't aimed at the consumers at all

threadripper, this CPU consumer can get as close as from server grade CPU
as far as I know threadripper SKU is based on epyc chips with some imperfection here and there

 

[HTC]

threadripper as close as consumer can get from server grade CPU
as far as I know threadripper SKU is based on epyc chips with some imperfection here and there

One imperfection is soon to be out of the way: the NUMA necessity (for chips that have more then 16 cores). There may be others that follow suite.

 

[stimpy88]

Exciting times, thanks to AMD! Interesting that they made no mention of IPC increases (there has to be some)... AMD mentioned a 2X performance increase from the previous generation Epyc, but considering that Rome has X2 the core count, this 2X performance number is a given.

This makes me conclude that Rome runs at at least 10% lower clocks than Naples.

This has me so excited for Zen2. X2 the floating point performance, PCIE-4, hopefully a 10% IPC uplift, and maybe even a couple of hundred MHz clock speed uptick to close the deal! Great stuff, take my money AMD!

 

[HTC]

Exciting times, thanks to AMD! Interesting that they made no mention of IPC increases (there has to be some)... AMD mentioned a 2X performance increase from the previous generation Epyc, but considering that Rome has X2 the core count, this 2X performance number is a given.

This makes me conclude that Rome runs at at least 10% lower clocks than Naples.

This has me so excited for Zen2. X2 the floating point performance, PCIE-4, hopefully a 10% IPC uplift, and maybe even a couple of hundred MHz clock speed uptick to close the deal! Great stuff, take my money AMD!

Could actually be even less because of TDP reasons, @ least for the 64c / 128t flagship: less core chips may likely have higher speeds, though.

 

[bug]

Exciting times, thanks to AMD! Interesting that they made no mention of IPC increases (there has to be some)... AMD mentioned a 2X performance increase from the previous generation Epyc, but considering that Rome has X2 the core count, this 2X performance number is a given.

This makes me conclude that Rome runs at at least 10% lower clocks than Naples.

This has me so excited for Zen2. X2 the floating point performance, PCIE-4, hopefully a 10% IPC uplift, and maybe even a couple of hundred MHz clock speed uptick to close the deal! Great stuff, take my money AMD!

Could actually be even less because of TDP reasons, @ least for the 64c / 128t flagship: less core chips may likely have higher speeds, though.

Frequencies are about the last thing to be set in stone for a CPU. AMD themselves don't know at this point how fast these will go. Unlike us, they have a ballpark figure though.

 

[stimpy88]

Frequencies are about the last thing to be set in stone for a CPU. AMD themselves don't know at this point how fast these will go. Unlike us, they have a ballpark figure though.

Very true, and they did stress that we were not seeing final production silicon. I would love AMD to claw back some more raw MHz on top of the new architecture, so as not to come out with lower clocks than Naples, but also keep it at a nice power and TDP level.

I suppose AMD want to keep the IPC improvements under their hat, as this 2X performance number was really like a Homer Simpson DOH! moment! Anything less than 2X performance, when core count is doubled, is a regression from Naples.

 

[Vayra86]

@lynx29 There you go buddy. If you still remember my discussion with you last week.

https://www.techpowerup.com/forums/...-horizon-event-scheduled.249151/#post-3934055

 

[R0H1T]

They stressed more about the power/performance characteristics of TSMC 7nm node. The final perf/W number could be higher/lower than 2x coming from Naples, since clocks aren't finalized yet & IPC is unknown.

 

[Vayra86]

Frequencies are about the last thing to be set in stone for a CPU. AMD themselves don't know at this point how fast these will go. Unlike us, they have a ballpark figure though.

Frequency is also the playground of product differentiation, besides XFR. And you can bet something is left in the tank if they can be competitive with a slightly lower clock.

 

[Mysteoa]

Perhaps is not functional, who knows?
So the chiplets were true, now let's wait the reviews.
Will these Rome be compatibles with the same motherboards as current EPYC?

Lisa said it is drop in replacement, they will just need to validate the board.

 

[bug]

Lisa said it is drop in replacement, they will just need to validate the board.

So it's a drop-in replacement that won't work on all boards? That's not a drop-in replacement, it's just reusing the socket where possible.
This is stuff people like to bash Intel about, but since you can't see into the future, you can never really guarantee a newly released CPU will work with boards built before it existed. So you must either change the socket (even if it's not really needed) or go through this revalidation, that may still leave you unable to use your old board if VRMs aren't up to the task or whatever.
Of course, you can reuse the socket if you stick to the exact same power spec. But more often than not, you're holding back the CPU by doing so.

Bottomline, reusing a socket is more complex than it seems. I'll happily take it when possible, but I won't fault chip makers when making me change the motherboard.

 

[stimpy88]

So it's a drop-in replacement that won't work on all boards? That's not a drop-in replacement, it's just reusing the socket where possible.
This is stuff people like to bash Intel about, but since you can't see into the future, you can never really guarantee a newly released CPU will work with boards built before it existed. So you must either change the socket (even if it's not really needed) or go through this revalidation, that may still leave you unable to use your old board if VRMs aren't up to the task or whatever.
Of course, you can reuse the socket if you stick to the exact same power spec. But more often than not, you're holding back the CPU by doing so.

Bottomline, reusing a socket is more complex than it seems. I'll happily take it when possible, but I won't fault chip makers when making me change the motherboard.

Don't you think it's most likely a BIOS related thing? I can't imagine the power requirements of this new CPU will increase much, and only by an amount that AMD specced in the VRM design specs for Naples. If there are any boards out there that have borderline VRM designs or components, then maybe that could cause an issue.

 

[bug]

Don't you think it's most likely a BIOS related thing? I can't imagine the power requirements of this new CPU will increase much, and only by an amount that AMD specced in the VRM design specs for Naples. If there are any boards out there that have borderline VRM designs or components, then maybe that could cause an issue.

Sometimes it can be fixed with a BIOS update. But even then, if you buy your new CPU together with an old board, not carrying the new BIOS, how do you flash it? There are workarounds, but sometimes they're simply not worth the hassle (for the manufacturer, that is).

Also, the BIOS update route tends to work between incremental updates like Sandy to Ivy Bridge. It's trickier when you need to squeeze more cores into the same power envelope with voltage and current already set in stone.

 

[Mysteoa]

Sometimes it can be fixed with a BIOS update. But even then, if you buy your new CPU together with an old board, not carrying the new BIOS, how do you flash it? There are workarounds, but sometimes they're simply not worth the hassle (for the manufacturer, that is).

Also, the BIOS update route tends to work between incremental updates like Sandy to Ivy Bridge. It's trickier when you need to squeeze more cores into the same power envelope with voltage and current already set in stone.

Since 7nm has 50% power reduction, adding 50% more cores gets you back to the same power envelope or close to. The other thing you need to consider is ROME has PCIeX 4 and I'm no sure how that will work with the current boards. We know Amd was already working on ROME/ ZEN2 while designing the socket so they could have made it to support 64 cores.