It has everything to do with that. No one gets on with the design of chip before they know what node it's going to be on.
It goes like this node -> architecture -> clock speeds. As you can see the manufacturing process is a defining factor for clock speeds.
I'm not sure how true that is.
Intel, AMD, NVIDIA, Samsung etc all measure power per mm^2, i.e power density is a key metric, not the clock frequency. The clock frequency comes way after they figure out what is the best performance per watt. So power per watt, must intersect with power per mm^2, when that target is reached, then clock frequencies may be adjusted accordingly. Power draw/consumption is affected by the manufacturing process, but that comes from the expected properties of the manufacturing node, from which the processor will be made.
Clock frequency is a target only after these two (power per mm^2, power per watt) have been worked out as clock frequency alone doesn't tell you anything about a processors computational abilities in isolation.
The design process at a high level, must make sense long before the node on which it will be manufactured on is a driving factor (how else could you work on a GPU for 10 years etc.). When engineers are drawing traces and laying out logic blocks etc. these do not always translate into how they will end up physically. for example traces can be wider or narrower in the silicon as opposed to when they were drawn on paper. This design and layout process can't wait for the node to exist first, it must work outside of that. Hence the back and fourth between these semiconductor firms and their fabs which is exhaustive.
Design validation is always first and you get that through simulation data both at the labs and at the fabs where it will be made. Clock frequencies can only be as high as what the power constraints allow, which is why that get's worked on first (power), not clock frequency.
Kepler and Maxwell were both on TSMC's 28nm process. What allowed the higher clock frequencies and lower power consumption (i.e power per watt and power per mm^2 was improved) was the logic changes in the design and layout, not the manufacturing improvements entirely. That extra 200~300MHz Maxwell could do over Kepler came from the changes made there primarily. While TSMC had improved their 28nm process, it wouldn't be enough to take Kepler as it is; add a billion transistors, increase the clock frequency and still hit the same power target. With all of those changes, areal density between these two increased by roughly ~ 5.4%, but clock speeds went up by nearly 20% on the same 28nm node. The heavy lifting in achieving this is outside of what TSMC's node manufacturing improvement alone could yield.