AMD X570 Chipset to Feature 40 PCIe 4.0 Lanes

[Raevenlord]

As we gear up for launch of AMD-s Ryzen 3000 series, details are bound to come up with increasing frequency. One of the latest, regarding AMD's in-house developed X570 chipset, which brings a renewed feature set to the AM4 platform, pertains to its PCIe lanes. AMD has included a grand total of 40 PCIe 4.0 lanes on the chipset, which will be distributed between PCIe uplink, USB 3.1 Gen2, USB 2.0 and SATA, as the spec sheet below (which may not be real) indicates. That's a whole load of bandwidth for the PC platform, not counting those PCIe lanes that are to be provided by the Ryzen CPUs.

It seems AMD will be using PCIe support level as a differentiator factor for its chipsets. The X570 is reported to be the only chipset to feature PCIe 4.0 support, while all other chipsets below it (B550 and so on) will only support PCIe 3.0. These lower-end chipsets should be manufactured by ASMedia.



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[Ebo]

WOW, sounds like I have found my new MB.

 

[moproblems99]

I believe other sources are reporting the that the B series chipsets will be PCIE 4.0 just not at launch. Or they will be delayed until 4.0 works for them.

 

[IceShroom]

Well I am only seeing 16 PCI-e Gen4 len not 40.

 

[ironwolf]

Well I am only seeing 16 PCI-e Gen4 len not 40.

The original article indicates that all the lanes in that chart are more or less added together to get the 40.

 

[R0H1T]

So those are chipset lanes?

 

[IceShroom]

The original article indicates that all the lanes in that chart are more or less added together to get the 40.

Well AMD's chipset dont work that way.
All I/O on chipset is discrete unlike Intel's chipset, thats means you cant convert USB to pcie lane.

 

[ironwolf]

Well AMD's chipset dont work that way.
All I/O on chipset is discrete unlike Intel's chipset, thats means you cant convert USB to pcie lane.

Simply going off the translation as I read it through Google Translate.

"but some of these 40 channels are shared with the sata interface."

 

[willace]

What.....B550 is not PCIE 4.0!!????

Why, just why?

 

[aQi]

Ok now im not an AMD kinda person but if im not wrong the pci revision is based on the processor not the motherboard itself. Just like Intel No ???

And more over PCIe 4.0 ? Does that even bother to exist where most peripherals not even manage to provide significant or perhaps a dramatic change ? The only utilisation iv seen from PCIe 2 to gen 3 are nvme speeds which itself are hardly noticeable...

Correct me if im wrong...

 

[Metroid]

I hope x570 price starts at $100 - $150, if is more than that then a x470 or lower am4 motherboard is the right choice.

 

[Mysteoa]

Ok now im not an AMD kinda person but if im not wrong the pci revision is based on the processor not the motherboard itself. Just like Intel No ???

And more over PCIe 4.0 ? Does that even bother to exist where most peripherals not even manage to provide significant or perhaps a dramatic change ? The only utilisation iv seen from PCIe 2 to gen 3 are nvme speeds which itself are hardly noticeable...

Correct me if im wrong...

The motherboard has to be certified to support PCIEX 4. The signaling requirements are different, so not all MB can do it.

It is more for marketing and bragging rights, 4 is bigger then 3. I don't see what curently will have benefit from it.

 

[Aquinus]

Those 4 lanes for uplink are disappointing, but not surprising. It's like a 4 to 40 PCIe switch, which is kind of sad but it's exactly what Intel has been doing with their PCHs for years. Honestly, it's what AMD has been doing ever since they ditched Hypertransport for communicating with the chipset. It's just the same old song and dance, but with a PCIe 4.0 sticker.

 

[Nihilus]

What.....B550 is not PCIE 4.0!!????

Why, just why?

Cost Savings? If you are running Rtx 2080ti or better, you are probably not getting a b-series.

 

[Mussels]

this should make a big difference for boards with more NVME slots, more USB 3.x/4.x etc (seriously the USB naming scheme is garbage)

 

[s3thra]

Nice, can't wait! I'm pretty excited with all the Zen 2 buzz.

It's good to see AMD on the front foot with PCIe 4.0 with the 500 series chipset (albeit only the X570 variant).

 

[TheLostSwede]

Let's try to clear things up a bit here.

First of all, the details in the leak appears to be correct from what I know and have known for several months and hinted at here before in other threads.

I don't know where the 40 PCIe lane rumour comes from, but unless you count the lanes in the CPU, it's not going to get anywhere close.
The chipset will have a significant amount of high-speed interfaces and if we use Intel naming, we can call it HSIO. I don't know if AMD will offer the same flexible IO as Intel does with its current PCH implementation, but it's a possibility. Even so, that doesn't make it 40 lanes.

The X570 chipset should be able to support at least two M.2 slots via the chipset and the new CPUs should still support a third M.2 slot that will be directly connected to the CPU, just as with the current Ryzen processors.
PCIe 4.0 SSDs are expected before the end of the year in retail. Expect early devices to be shown at Computex.

Technically the x16 slot from the CPU and the M.2 slot from the CPU when it comes to Ryzen 3000 parts (not counting the APUs), will support PCIe 4.0 on any board, as long as it has been designed to meet the speeds. Not all current boards will be capable of doing this, but some boards might be able to support PCIe 4.0 for those two ports. This also applies to a potential future B550 chipset.

Note that not all X570 boards will fully support PCIe 4.0 either, due to the cost of the PCIe 4.0 retimer/redriver/repeater whatever it is that is required to make PCIe 4.0 work. This will also depend on chipset placement on the boards and a few other things. PCIe 4.0 is apparently not that easy to design in on the ATX motherboard form factor, as the trace lengths easily get too long and the signal degrades. We might end up getting to see some interesting board layouts to try and make PCIe 4.0 work better, but judging by the presumed board picture from Biostar that has made the rounds, this might not be the case. Note that Biostar has covered up the picture on their site since then https://www.biostar.com.tw/app/en/news/news.php?S_ID=361

As AMD doesn't have an integrated Ethernet MAC in their chipsets, at least one PCIe lane will be used for Ethernet.

Those 4 lanes for uplink are disappointing, but not surprising. It's like a 4 to 40 PCIe switch, which is kind of sad but it's exactly what Intel has been doing with their PCHs for years. Honestly, it's what AMD has been doing ever since they ditched Hypertransport for communicating with the chipset. It's just the same old song and dance, but with a PCIe 4.0 sticker.

So you mean exactly what Intel does with their PCH and DMI? Let's wait and see though, as there might be more to it than this leak details.

 

[Aquinus]

So you mean exactly what Intel does with their PCH and DMI? Let's wait and see though, as there might be more to it than this leak details.

DMI is just an over-glorified PCIe-like implementation, AMD is no different. Both camps have already been doing this. What I'm seeing is more of the same and I seriously doubt there is more to it if this is how they've been doing things already.

 

[TheLostSwede]

DMI is just an over-glorified PCIe-like implementation, AMD is no different. Both camps have already been doing this. What I'm seeing is more of the same and I seriously doubt there is more to it if this is how they've been doing things already.

Well, yes, hence my point. However, there might be more to AMD's X570 than what's been revealed so far and the chipset might have a wider bus than this leak implies, but that's a maybe, based on some old info I have been sitting on for the past six months.

 

[Aquinus]

Well, yes, hence my point. However, there might be more to AMD's X570 than what's been revealed so far and the chipset might have a wider bus than this leak implies, but that's a maybe, based on some old info I have been sitting on for the past six months.

Except that there is absolutely nothing to indicate that they're going to change this aspect of their chipsets, so it's more reasonable to assume that it's not going to change. Considering the root PCIe complex is still on the CPU, I seriously doubt that this will change. The only reason to do this is to allow for more connectivity, not to make it faster.

 

[TheLostSwede]

Except that there is absolutely nothing to indicate that they're going to change this aspect of their chipsets, so it's more reasonable to assume that it's not going to change. Considering the root PCIe complex is still on the CPU, I seriously doubt that this will change. The only reason to do this is to allow for more connectivity, not to make it faster.

That you know of, yes. But as I said, let's wait and see. I don't think it's too likely, but it's a potential improvement from the previous two generations of chipsets. I never said it wasn't going to be PCIe though, that was your assumption...

 

[Aquinus]

That you know of, yes. But as I said, let's wait and see. I don't think it's too likely, but it's a potential improvement from the previous two generations of chipsets. I never said it wasn't going to be PCIe though, that was your assumption...

It's not an assumption though. All of the AM4 chipsets use 4 PCIe lanes to communicate with the CPU. That's not a fact in dispute. Intel's DMI is just that, 4 PCIe lanes to the CPU but with a fancy name.

 

[jabbadap]

It's not an assumption though. All of the AM4 chipsets use 4 PCIe lanes to communicate with the CPU. That's not a fact in dispute. Intel's DMI is just that, 4 PCIe lanes to the CPU but with a fancy name.

Well yeah, at least it's pcie gen4 so speed doubles from 1st/2nd gen Ryzens.

 

[TheLostSwede]

It's not an assumption though. All of the AM4 chipsets use 4 PCIe lanes to communicate with the CPU. That's not a fact in dispute. Intel's DMI is just that, 4 PCIe lanes to the CPU but with a fancy name.

Why are you having an argument with yourself? You need to learn to read, as I've never said anything else. The only thing I mentioned, is that things might be different this time around.

Well yeah, at least it's pcie gen4 so speed doubles from 1st/2nd gen Ryzens.

But at the same time, the peripheral interfaces has more than tripled, which puts more pressure on the CPU to chipset interface. On top of that, AMD has increased the lane count for peripherals in the chipset...

 

[mat9v]

40 lines is combined:
CPU - 16 (GPU) + 4 (NVMe) + 4 (downlink to chipset) = 24
Chipset (8+4+4) = 16 (of those 4+4 can be used to extend default 4 SATA config to 6 SATA config - just like in Ryzen 1xxx and 2xxx chipsets)
Together you get 40 lines. It's unfortunately like Intel marketing where they combine CPU and Chipset lines. Sad but true.
B550 according to original story do have PCIEx 4.0 - they are having some problems on some boards, but chipset as it is does have it implemented.