You know, Rome is doing just fine without exaggerations.
- Power-wise the thread count comparison might be apt but leaving that aside for the moment even current Xeon 9200 do work with 2-socket resulting in 224 threads.
- According to the leaked list, 64-core Romes are 200W and 225W. Hopefully AMD is not doing the same thing as Ryzen 3000 series has on the desktop where default settings are +35% to that.
- 128 PCI-e lanes each means 128 PCI-e lanes total for dual-socket configuration or as servethehome speculates, perhaps 160 with generational improvements. Intel is not doing better - usual, up to 28 core, Xeons have 48 lanes per CPU (96 lanes for dual) and Xeon 9200 has 40 lanes per CPU (80 lanes for dual).
Architecture is not the problem. Power and 14nm is Intel's problem today. If they are stuck with this until they can figure out how 10nm works or if they have another approach, we'll see.
Couple of notes:
Rome boards are designed with expectation of 250w/socket, either for milan or for turbo, reviews will tell.
128 lanes of PCIE 4 per cpu, or when configured in dual cpu mode half the lanes are coordinated as XGMI links which are x16 links but a more efficient protocol giving lower latency and higher bandwidth.
Server makers can opt to use 3 or 4 XGMI links giving an extra possible 32 lanes but that would sacrifice inter-socket bandwidth while increasing the needs for it. I think its a bad play as 128 pcie 4 lanes is a shitton of bandwidth...
Intel 9200 is BGA and boards and chips have to be bought from intel its a 200k sort of play without ram... and almost no one is buying first gen. It draws too much power, there is no differentiation to be had between vendors... it's just not a good thing. Intel has sort of listened and made a gen2 with cooperlake being socketed and upgradable to icelake.
Comparing 9200 and rome is not useful as it's not really in the market. Intel having 96 pcie 3.0 lanes vs 128-160 pcie 4.0 lanes is just an insane bandwidth difference. As far as server config is concerned I expect many single proc rome servers, and most dual proc to be configured with 3 xgmi links.
Intel will retail single threaded performance advantage in the server realm most likely, but will be dominated in anything that can use the insane amount of threads AMD is offering.
As far as what Keller is working on... he is VP of SOC and is working on die stacking and other vertical highly integrated density gains...
He claiming 50x density improvements over 10nm and it is "virtually working already"
