So you see the problem? Bulldozer "execution cores" lack the hardware to decode AMD64 instructions which is a function of the "core" (aka processor). "Execution cores" as defined in Bulldozer lack the hardware necessary to be considered a "core:" they are merely "execution units." ...and these are the wheels the turn the gears of false advertising.
"More specifically, this invention relates to processors that convert an x86 instructions into RISC-type operations for execution on a RISC-type core."
"The core of the processor is a RISC superscalar processing engine."
"The heart of the AMD-K6 processor is a RISC core known as the enhanced RISC86 microarchitecture."
"The AMD-K5 processor’s superscalar RISC core consists of six execution units: two arithmetic logic units (ALU), two load/store units, one branch unit, and one floating-point unit (FPU). This superscalar core is fully decoupled from the x86 bus through the conversion of variable-length x86 instructions into simple, fixed-length RISC operations (ROPs) that are easier to handle and execute faster. Once the x86 instruction has been converted, a dispatcher issues four ROPs at a time to the superscalar core. The processor’s superscalar core can execute at a peak rate of six ROPs per cycle. The superscalar core supports data forwarding and data bypassing to immediately forward the results of an execution to successive instructions."
"AMD-K6 MMX Processor : High-performance RISC core : Yes / 6-issue (RISC86)"
"The execution engine implements a superscalar, out-of-order, reduced instruction set computing (RISC) architecture"
"The dual instruction decoders translate X86 instructions on-the-fly into corresponding RISC86 Ops. The RISC86 Ops are executed by an instruction core that is essentially a RISC superscalar processing engine."
"From the viewpoint of packing multiple primitive operations into a coarser schedulable unit and performing schedule and execution of macro-ops, the proposed microarchitecture employs a counter approach to recent x86 processor implementations that crack a CISC instruction and convert it into multiple RISC semantics running on RISC-style cores."
"As a coarser-grained approach in the opposite direction, the AMD K7 and the Intel Pentium M have adopted techniques to allow an issue queue entry to accommodate multiple micro-ops as a form of fused operations for certain types of x86 instructions. Original micro-ops are loosely coupled in a fused operation from the scheduler’s perspective; they are scheduled individually according to the readiness of corresponding source operands."
RISC86 which poorly interpreted x86 to Macro-ops which were better interpreted for x86.
"AMD-K7 ™ Processor Architecture => Three Parallel x86 Instruction Decoders => Decoding Pipelines can dispatch 3 MacroOps to Execution Unit Schedulers, Load / Store Queue Unit => Result Busses from Core"
^-- this one is the most intriguing as the only mention of a core is for the LSU slide.
"The AMD Athlon processor microarchitecture is a decoupled decode/execution design approach. In other words, the decoders essentially operate independent of the execution units, and the execution core uses a small number of instructions and simplified circuit design for fast single-cycle execution and fast operating frequencies."
Then, K8 happens... oh dear...
"The AMD64 architecture employs a decoupled decode/execution design approach. In other words, decoders and execution units essentially operate independently; the execution core uses a small number of instructions and simplified circuit design for fast single-cycle execution and fast operating frequencies."
"The AMD Athlon 64 and AMD Opteron processors implement the AMD64 instruction set by means of micro-ops—simple fixed-length operations designed to include direct support for AMD64 instructions and adhere to the high-performance principles of fixed-length encoding, regularized instruction fields, and a large register set. The enhanced microarchitecture enables higher processor core performance and promotes straightforward extensibility for future designs"
That is all dandy, but then it explodes: CPU cores, cores, processor cores, etc. Which isn't the core they originally defined; "This superscalar core is fully decoupled from the x86 bus through the conversion of variable-length x86 instructions into simple, fixed-length RISC operations (ROPs) that are easier to handle and execute faster."
"A processor core for supporting the concurrent execution of mixed integer and floating point operations includes integer functional units utilizing 32-bit operand data and a floating point functional unit utilizing up to 82-bit operand data."
"FIG. 13 is a schematic diagram of a layout of a mixed floating point/integer processor core"
