Samsung Develops Industry's First 12-Layer 3D-TSV Chip Packaging Technology

[btarunr]

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced that it has developed the industry's first 12-layer 3D-TSV (Through Silicon Via) technology. Samsung's new innovation is considered one of the most challenging packaging technologies for mass production of high-performance chips, as it requires pinpoint accuracy to vertically interconnect 12 DRAM chips through a three-dimensional configuration of more than 60,000 TSV holes, each of which is one-twentieth the thickness of a single strand of human hair.

The thickness of the package (720 µm) remains the same as current 8-layer High Bandwidth Memory-2 (HBM2) products, which is a substantial advancement in component design. This will help customers release next-generation, high-capacity products with higher performance capacity without having to change their system configuration designs. In addition, the 3D packaging technology also features a shorter data transmission time between chips than the currently existing wire bonding technology, resulting in significantly faster speed and lower power consumption.



"Packaging technology that secures all of the intricacies of ultra-performance memory is becoming tremendously important, with the wide variety of new-age applications, such as artificial intelligence (AI) and High Power Computing (HPC)," said Hong-Joo Baek, executive vice president of TSP (Test & System Package) at Samsung Electronics.

"As Moore's law scaling reaches its limit, the role of 3D-TSV technology is expected to become even more critical. We want to be at the forefront of this state-of-the-art chip packaging technology."

Relying on its 12-layer 3D-TSV technology, Samsung will offer the highest DRAM performance for applications that are data-intensive and extremely high-speed.

Also, by increasing the number of stacked layers from eight to 12, Samsung will soon be able to mass produce 24-gigabyte (GB)* High Bandwidth Memory, which provides three times the capacity of 8GB high bandwidth memory on the market today.

Samsung will be able to meet the rapidly growing market demand for high-capacity HBM solutions with its cutting-edge 12-layer 3D TSV technology and it hopes to solidify its leadership in the premium semiconductor market.

View at TechPowerUp Main Site

 

[HD64G]

Intel might be another main reason for that, apart from HBM RAM chips' packaging. 2022 in the earliest for the sale of anything related to this manufacturing method.

 

[kapone32]

Wondering if this will be memory for the "Big Navi".

 

[fynxer]

Hope standard HBM memory will start to drop in price so we can get them in all high end gaming cards.

 

[The Egg]

Wondering if this will be memory for the "Big Navi".

Uh.....I would hope "Big Navi" is further along in development than designing around a memory technology that was just announced today.

 

[kapone32]

Uh.....I would hope "Big Navi" is further along in development than designing around a memory technology that was just announced today.

I know what you mean but while we are just learning of this today. Companies with agreements (like AMD) may have already been privy to this information.

 

[The Egg]

I know what you mean but while we are just learning of this today. Companies with agreements (like AMD) may have already been privy to this information.

If Navi 12 is going into production anytime soon, they would've needed to start taping-out roughly a year ago. The actual chip design was probably 2 years ago.

I doubt you'll see this in an actual shipping product anytime before 2021, and even that might be optimistic.

 

[TechLurker]

I wonder if this upgraded stack would potentially allow for AMD to add one in to feed the GPU side of their APUs, or for some setups where one later adds in a dedicated GPU, allow for disabling of the onboard GPU and using the HBM instead for the CPU as L4 cache.