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The "Willow Cove" CPU core design succeeds "Sunny Cove," Intel's first truly new CPU core design in close to 5 years. "Sunny Cove" is implemented in the 10 nm "Ice Lake" microarchitecture, and "Willow Cove" cores are expected to debut with the 10 nm+ "Tiger Lake." It turns out that Intel is working to adapt "Willow Cove" CPU cores onto a 14 nm microarchitecture, and "Rocket Lake" could be it.
Twitter user @chiakokhua, a retired VLSI engineer with high hit-rate on CPU microarchitecture news, made sense of technical documents to point out that "Rocket Lake" is essentially a 14 nm adaptation of "Tiger Lake," but with the iGPU shrunk significantly, to make room for the larger CPU cores. The Gen12 iGPU on "Rocket Lake-S" will feature just 32 execution units (EUs), whilst on "Tiger Lake," it has three times the muscle, with 96 EUs. "Rocket Lake" also replaces "Tiger Lake's" FIVR (fully-integrated voltage regulation) with a conventional SVID VRM architecture.
We know from an older report that the 14 nm "Rocket Lake-S" silicon has up to 8 CPU cores, even as its predecessor, "Comet Lake-S," dials core-counts up to 10. We know now that the lowered core count is a trade-off for big IPC gains. For the desktop platform, "Rocket Lake-S" could herald the first major IPC uplift on the Intel platform since "Skylake."
View at TechPowerUp Main Site
Twitter user @chiakokhua, a retired VLSI engineer with high hit-rate on CPU microarchitecture news, made sense of technical documents to point out that "Rocket Lake" is essentially a 14 nm adaptation of "Tiger Lake," but with the iGPU shrunk significantly, to make room for the larger CPU cores. The Gen12 iGPU on "Rocket Lake-S" will feature just 32 execution units (EUs), whilst on "Tiger Lake," it has three times the muscle, with 96 EUs. "Rocket Lake" also replaces "Tiger Lake's" FIVR (fully-integrated voltage regulation) with a conventional SVID VRM architecture.
We know from an older report that the 14 nm "Rocket Lake-S" silicon has up to 8 CPU cores, even as its predecessor, "Comet Lake-S," dials core-counts up to 10. We know now that the lowered core count is a trade-off for big IPC gains. For the desktop platform, "Rocket Lake-S" could herald the first major IPC uplift on the Intel platform since "Skylake."
View at TechPowerUp Main Site