- Joined
- Aug 19, 2017
- Messages
- 2,654 (0.99/day)
During the IEDM event hosted by the IEEE organization, ASML's CEO, Martin van den Brink, took the stage to elaborate more on ASML's vision of the future of semiconductors. When talking about the future of semiconductors, Mr. Brink started talking about Intel and their vision for the future. Intel's slides were showing many things including backporting of IP to older processes and plan to go back to "tick-tock" two-year cadence to restore the previous confidence in Intel's manufacturing capabilities.
Perhaps one of the most interesting notes about the presentation is the fact that Intel is working hard to realize its plans of bringing back a two-year cadence of "tick-tock" process realization. That means that in the future, presumably after 10 nm debut problems are solved, Intel wants to do the old process and optimization tactics. A slide (shown below) titled "In Moore We Trust" is speaking a lot about Intel's future plans, showing few things in particular: Intel's upcoming 10 nm++ and 10 nm+++ nodes, and the possibility of backporting.
When it comes to 10 nm++ and 10 nm+++ nodes, Intel is displaying that they are already working on improved versions of 10 nm+ node used in Ice Lake chips so that new and improved versions of 10 nm node will be ready for higher frequencies and better performance. The current version of 10 nm+ node is not very capable frequency wise, as there is currently only one Ice Lake SKU that can reach 4 GHz, while current 14 nm products are capable of reaching 5 GHz with ease. These upcoming nodes are supposed to address this problem by providing faster transistors.
Additionally, backporting is now going to node manufacturing, not IP only anymore. So far Intel spoke of backporting as a means to deliver new IP built for 10 nm for example to older process like 14 nm if needed. However, the new slide shows the intention of Intel to apply backporting techniques to a semiconductor process. For example, 7 nm can get backported to 10 nm node in form of 10 nm+++ so that it still officially is 10 nm by Intel's standards, but features overall transistor improvements that were supposed to be released on 7 nm node.
Intel is also developing new nodes that are going to be released as far as ten years from now. Shown above is the 1.4 nm node, scheduled for release in 2029 when it will supposedly be launched. The 1.4 nm node is supposed to have a density of 1.6 billion transistors per square millimeter, which is equivalent to many of the early 14 nm Broadwell CPUs. It is unimaginable to think about such distant technologies now, plus, as the roadmap shows, all the information displayed is subject to change.
View at TechPowerUp Main Site
Perhaps one of the most interesting notes about the presentation is the fact that Intel is working hard to realize its plans of bringing back a two-year cadence of "tick-tock" process realization. That means that in the future, presumably after 10 nm debut problems are solved, Intel wants to do the old process and optimization tactics. A slide (shown below) titled "In Moore We Trust" is speaking a lot about Intel's future plans, showing few things in particular: Intel's upcoming 10 nm++ and 10 nm+++ nodes, and the possibility of backporting.
When it comes to 10 nm++ and 10 nm+++ nodes, Intel is displaying that they are already working on improved versions of 10 nm+ node used in Ice Lake chips so that new and improved versions of 10 nm node will be ready for higher frequencies and better performance. The current version of 10 nm+ node is not very capable frequency wise, as there is currently only one Ice Lake SKU that can reach 4 GHz, while current 14 nm products are capable of reaching 5 GHz with ease. These upcoming nodes are supposed to address this problem by providing faster transistors.
Additionally, backporting is now going to node manufacturing, not IP only anymore. So far Intel spoke of backporting as a means to deliver new IP built for 10 nm for example to older process like 14 nm if needed. However, the new slide shows the intention of Intel to apply backporting techniques to a semiconductor process. For example, 7 nm can get backported to 10 nm node in form of 10 nm+++ so that it still officially is 10 nm by Intel's standards, but features overall transistor improvements that were supposed to be released on 7 nm node.
Intel is also developing new nodes that are going to be released as far as ten years from now. Shown above is the 1.4 nm node, scheduled for release in 2029 when it will supposedly be launched. The 1.4 nm node is supposed to have a density of 1.6 billion transistors per square millimeter, which is equivalent to many of the early 14 nm Broadwell CPUs. It is unimaginable to think about such distant technologies now, plus, as the roadmap shows, all the information displayed is subject to change.
View at TechPowerUp Main Site
