Intel Zooms in on "Lakefield" Foveros Package

[btarunr]

The fingernail-size Intel chip with Foveros technology is a first-of-its kind. With Foveros, processors are built in a totally new way: not with the various IPs spread out flat in two dimensions, but with them stacked in three dimensions. Think of a chip designed as a layer cake (a 1-millimeter-thick layer cake) versus a chip with a more-traditional pancake-like design. Intel's Foveros advanced packaging technology allows Intel to "mix and match" technology IP blocks with various memory and I/O elements - all in a small physical package for significantly reduced board size. The first product designed this way is "Lakefield," the Intel Core processor with Intel hybrid technology.

Industry analyst firm The Linley Group recently named Intel's Foveros 3D-stacking technology as "Best Technology" in its 2019 Analysts' Choice Awards. "Our awards program not only recognizes excellence in chip design and innovation, but also acknowledges the products that our analysts believe will have an impact on future designs," said Linley Gwennap, of The Linley Group.



For its part, Lakefield represents an entirely new class of chip. It delivers an optimal balance of performance and efficiency with best-in-class connectivity in a small footprint - Lakefield's package area measures just 12-by-12-by-1 millimeters. Its hybrid CPU architecture combines power-efficient "Tremont" cores with a performance scalable 10 nm "Sunny Cove" core to intelligently deliver productivity performance when needed and power-sipping efficiency when not needed for long battery life.

These benefits offer original equipment manufacturers more flexibility for thin-and-light form factor PCs, including the emerging dual-screen and foldable screen PC categories.

Recently, three designs have been announced that are powered by Lakefield and were co-engineered with Intel. In October 2019, Microsoft previewed the Surface Neo, a dual-screen device. And later that month at its developer conference, Samsung announced the Galaxy Book S. Unveiled at CES 2020 and expected to ship midyear is the Lenovo ThinkPad X1 Fold.

View at TechPowerUp Main Site

 

[Flanker]

With Foveros, processors are built in a totally new way: not with the various IPs spread out flat in two dimensions, but with them stacked in three dimensions.

Wouldn't that make it a lot harder to cool the chip?

 

[R0H1T]

Wouldn't that make it a lot harder to cool to chip?

Yes of course, in fact cooling is the biggest challenge as we get close to that magical 1nm (marketing) number!

 

[Fouquin]

Wouldn't that make it a lot harder to cool the chip?

Correct. There have been a number of patents filed since 2011 that detail 3D stacked cooling in the form of TEC layers and TSVs.

 

[R0H1T]

cooling in the form of TEC

Which in reality never works in the way as advertised.
Anyway Feveros or any other 3d stacking has real limitations, for instance I don't see a 1650 super equivalent being paired with a 10900k in package & still be able to perform at its optimal best.

 

[Fouquin]

Which in reality never works in the way as advertised.
Anyway Feveros or any other 3d stacking has real limitations, for instance I don't see a 1650 super equivalent being paired with a 10900k in package & still be able to perform at its optimal best.

There's nothing advertised, just technology patented. The technology clearly works and has been explored by IBM, AMD, Intel and Samsung. The question that remains is how it will scale, and what combination of techniques will be required to achieve desirable results.

 

[Midland Dog]

Which in reality never works in the way as advertised.
Anyway Feveros or any other 3d stacking has real limitations, for instance I don't see a 1650 super equivalent being paired with a 10900k in package & still be able to perform at its optimal best.

TEC cooling is pretty stupid considering that in this instance its going to be between sillicon and by its nature has a hot side, thus heating up the chips above it

 

[R0H1T]

There's nothing advertised, just technology patented. The technology clearly works and has been explored by IBM, AMD, Intel and Samsung. The question that remains is how it will scale, and what combination of techniques will be required to achieve desirable results.

You're talking about TEC right? Because I am & it's been advertised way before any patent Intel may have filed, especially in conjunction with Feveros.
It simply doesn't work the way it's portrayed & if it isn't TEC then perhaps you could link us to the said patent or cooling technology?

 

[Fouquin]

TEC cooling is pretty stupid considering that in this instance its going to be between sillicon and by its nature has a hot side, thus heating up the chips above it

Some integrated blocks don't have such stringent thermal limits, such as multi-phase regulators, sensor arrays, and low-output control logic. Sinking heat to them from adjacent blocks that cannot handle higher temperatures isn't unheard of.

You're talking about TEC right? Because I am & it's been advertised way before any patent Intel may have filed, especially in conjunction with Feveros.

Correct. The problem is you're thinking of TEC in the context of those $4 ceramic packages you buy on eBay from some random cart stall in Shenzhen. TEC has a well documented and very precise efficiency curve, or cliff in most cases. Applying it sparingly while catering to the efficiency point can provide controllable thermal management.

US7893529B2 - Thermoelectric 3D cooling - Google Patents

The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips.

patents.google.com

http://www.freepatentsonline.com/10210912.html

US20130119528A1 - Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods - Google Patents

Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first...

patents.google.com

Also here's a great read on how achievable 3D stacking is even without exotic thermal management.

http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.130.6198&rep=rep1&type=pdf

 

[londiste]

Which in reality never works in the way as advertised.
Anyway Feveros or any other 3d stacking has real limitations, for instance I don't see a 1650 super equivalent being paired with a 10900k in package & still be able to perform at its optimal best.

I don't think anyone is trying to use 3D stacking for high-power/performance chips at this point. Intel is presenting mobile stuff with Foveros and this is what 3D stacking is primarily aimed at. Dissipating 20-30W from a stack shouldn't be that much of a problem if they try to position dies with thermals in mind. And so far, they have been showing under 10W designs.

 

[notb]

Which in reality never works in the way as advertised.

Stacked products exist and will go mainstream this year. I'm not sure why we're still discussing whether cooling works or not.

Anyway Feveros or any other 3d stacking has real limitations, for instance I don't see a 1650 super equivalent being paired with a 10900k in package & still be able to perform at its optimal best.

Every technology has limits.
Stacking high power chips makes no sense and is unlikely to happen, ever. That's not the target product segment.

 

[Vya Domus]

Intel is presenting mobile stuff with Foveros and this is what 3D stacking is primarily aimed at.

I can't see how 3D stacking is aimed at anything to be honest. Mobile chips are low performance and cheap to begin with and I seriously doubt 3D stacking reduces their cost in any way, if anything it's probably significantly more expensive, so in most applications you wouldn't want to touch them. Size wise the gains are trivial, most SoCs are highly integrated anyway. This is presented as a solution to a problem that doesn't really exist.

 

[notb]

I can't see how 3D stacking is aimed at anything to be honest.

Well, you're not a large company involved in this industry and investing millions in this idea. You're not expected to see how.

Mobile chips are low performance and cheap to begin with and I seriously doubt 3D stacking reduces their cost in any way, if anything it's probably significantly more expensive, so in most applications you wouldn't want to touch them. Size wise the gains are trivial, most SoCs are highly integrated anyway.

Mobile chips are neither low performance nor cheap. They're just scaled - smaller than what you use in your desktop.
And of course stacking will make chips more expensive.

Size gains are anything but trivial. Mobile packages are enormous - especially when a more powerful GPU is added to the mix.
Moreover, Foveros is not just about the SoC. It also includes RAM - effectively (at least) halving the total area of these components on a PCB.

This is presented as a solution to a problem that doesn't really exist.

Or you just don't understand the problem?

 

[Tomorrow]

Intel's problem is not making cool products or even just annoucements. It's about being able to to produce them in scale.
So while Lakefield looks cool it's essentially a paperweight until it's widely available. Make it happen Intel!

 

[R0H1T]

Stacked products exist and will go mainstream this year. I'm not sure why we're still discussing whether cooling works or not.

Every technology has limits.
Stacking high power chips makes no sense and is unlikely to happen, ever. That's not the target product segment.

I guess you forgot about this using 3d stacking, no surprises here
Intel Xe Graphics to Feature MCM-like Configurations, up to 512 EU on 500 W TDP

 

[notb]

I guess you forgot about this using 3d stacking, no surprises here
Intel Xe Graphics to Feature MCM-like Configurations, up to 512 EU on 500 W TDP

You said about pairing a dGPU with a CPU (I assumed: stacking, why mention it here otherwise?).
Xe will stack computing cores with memory - not computing layers.
In fact, once their get this technology cheap, there's not reason not to use it as much as possible. So we should see stacked CPU caches as well.