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Rambus Designs HBM2E Controller and PHY

AleksandarK

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Rambus, a maker of various Interface IP solutions, today announced the latest addition to its high-speed memory interface IP product portfolio in form of High Bandwidth Memory 2E (HBM2E) controller and physical layer (PHY) IP solution. The two IPs are enabling customers to completely integrate the HBM2E memory into their products, given that Rambus provides a complete solution for controlling and interfacing the memory. The design that Ramus offers can support for 12-high DRAM stacks of up to 24 Gb devices, making for up to 36 GB of memory per 3D stack. This single 3D stack is capable of delivering 3.2 Gbps over a 1024-bit wide interface, delivering 410 GB/s of bandwidth per stack.

The HBM2E controller core is DFI 3.1 compatible and has support for logic interfaces like AXI, OCP, or a custom one, so the customer can choose a way to integrate this core in their design. With a purchase of their HBM2E IP, Rambus will provide source code written in Hardware Description Language (HDL) and GDSII file containing the layout of the interface.


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Surely we'll see in 6-8 months time, that Rambus has decided to sue Rambus for patent infringement??


:shadedshu:
 

Aquinus

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I've been waiting for something like this to come around. This could be great for mobile devices where space is at a premium or with SoCs with a relatively powerful iGPU, or both.
 
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I've been waiting for something like this to come around. This could be great for mobile devices where space is at a premium or with SoCs with a relatively powerful iGPU, or both.

You will have to wait some more until HBM became cheap and produced in large volume.
 
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Did they get a patent for it?
 
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Did they get a patent for it?

The fact that they are talking about IP enabling this that, and fully custom interface... Aka we are going to sue everyone for the next 25 years.

Sigh...

There goes HBM getting any cheaper. They'll somehow sue everyone because HBM19 will still somehow use something they patented in this. That custom interface says it all, they are covering designs they haven't even thought of.

Bah!
 
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I bet it causes 3rd degree burns, and Intel will use it only to drop it later, b/c performance is lower than DDR4 :D
 
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