AMD "Renoir" Desktop APU Could Lack PCIe gen 4.0, Hints BIOSTAR B550 Motherboard Product Page

[btarunr]

AMD's 4th generation Ryzen "Renoir" desktop APUs, based on the "Zen 2" microarchitecture, could lack PCI-Express gen 4.0, hints the product page of an upcoming AMD B550 chipset motherboard by BIOSTAR. AMD already declared that the B550 lacks support for "Picasso," which means the "Ryzen with Radeon Vega Graphics" processors referenced in the BIOSTAR product page have to be "Renoir." On the mobile platform, Ryzen 4000H and 4000U series processors do lack PCIe gen 4.0, but it was expected that AMD will enable gen 4.0 for the desktop socket AM4 platform.

The lack of gen 4.0 support has implications for "Renoir." For starters, the APU, like its predecessors, spares only 8 PCIe lanes toward PEG (PCI-Express discrete graphics, or the main x16 slot you typically use for graphics cards). If these lanes are gen 3.0, then even the newer graphics cards, such as AMD's "Navi" RX 5700 XT, or next-gen GeForce "Ampere," would have to make do with a PCI-Express 3.0 x8 interface, despite being gen 4.0 x16-capable. We will test just how much of a bottleneck this poses, when the next-gen graphics cards come out.



The second implication specifically affects the platform. On some upcoming motherboards, such as the B550 AORUS Master by GIGABYTE, PCIe gen 4.0 lanes from the PEG slot are shared with a couple of additional M.2 slots. So, you'd be left with only one of the three M.2 slots functional, the topmost one that's directly wired to the AM4 socket, and at gen 3.0 speeds. Lastly, the lack of gen 4.0 means that the chipset-bus between "Renoir" and both the B550 and X570 will be PCI-Express 3.0 x4. With "Matisse" or "Vermeer," the bus runs at PCI-Express 4.0 x4 speeds.

View at TechPowerUp Main Site

 

[R0H1T]

What ~ stop the presses, where's my pitchforks torches

 

[GoldenX]

This was a way to mitigate the missing 8 lines... Bad move.

 

[mainlate]

AMD´s intentional crippling of own products. Even Coffee Lake Celeron´s have 16x...gen 3.0 but still 16x.

 

[olstyle]

AMD clearly stated on the notebook release that Renoir was designed that way to reduce power consumption. PCIe 4.0 was not disabled but left out completely.
Since, different to Intel, AMD does not produce more differing wafer masks than absolutely necessary it is very probable that desktop Renoir is completely the same silicon as the notebook one, resulting in PCIe 3.0 just being all there is inside the chip.

 

[AlB80]

Wrong assumption.
B550 description is copypasted from X570 board. X570 supports Picasso and Raven ridge.

 

[Melvis]

Who cares? like really?

 

[Tom Yum]

AMD clearly stated on the notebook release that Renoir was designed that way to reduce power consumption. PCIe 4.0 was not disabled but left out completely.
Since, different to Intel, AMD does not produce more differing wafer masks than absolutely necessary it is very probable that desktop Renoir is completely the same silicon as the notebook one, resulting in PCIe 3.0 just being all there is inside the chip.

Renoir also supports 16 PCIE 3.0 lanes instead of the 12 Picasso supported. It makes sense that the same die would retain the same IO regardless of socket.

Also, I'm not sure the underlying assumption (B550 doesn't support Picasso) applies. The blogosphere seemed to ignore that despite AMD not supporting 3rd gen Ryzen on 1st gen AM4 chipsets like x370/b350 boards, most of those boards received and supported 3rd gen Ryzen bios updates no problem. It is therefore quite likely motherboard manufacturers will provide unofficial support to older processors and therefore that guidance may be directed at Picasso, and will be updated when Renoir on desktop is actually released.

 

[AlB80]

Also, I'm not sure the underlying assumption (B550 doesn't support Picasso) applies.

It's not my assumption.

btarunr > AMD already declared that the B550 lacks support for "Picasso," which means the "Ryzen with Radeon Vega Graphics" processors referenced in the BIOSTAR product page have to be "Renoir." On the mobile platform, Ryzen 4000H and 4000U series processors do lack PCIe gen 4.0, but it was expected that AMD will enable gen 4.0 for the desktop socket AM4 platform.

 

[Chrispy_]

I'm not surprised if this turns out to be true.

Renoir is a mobile part, first and foremost, and the X570 with PCIe 4.0 demands active cooling for its 15-20W power draw. That kind of power consumption has no part being within a mile of any parts aimed at the 15W laptop market.

I don't know how much power CPU PCIe 4.0 on the existing Picasso dies uses, but based on the chipset draw, I'm going to take a guess that it's not trivial.

 

[AnarchoPrimitiv]

Can we please address the double standard toward AMD here? The first commentor hit the nail on the head.... Why does everyone feel entitled to AMD doing everything they want? They don't act this way toward Nvidia and Intel? I guarantee if that whole X470 not supporting Zen3 thing was done by Intel, everyone would have just went "meh". I'm not defending AMD here, I'm pointing out hypocrisy and a double standard because I cannot stand them.

It's almost as if all these people somehow expect AMD to compete against Intel and Nvidia while somehow not doing any of the competitive actions Intel and Nvidia does... You can't have it both ways..... Either AMD competes at the highest level with cutthroat tactics, or (as a lot of people have acted lately) they're a non-profit charity solely created to fulfill the every whim of whatever "enthusiast" whines the loudest and as a ridiculous sense of entitlement.

Here's my first point: why would an APU, designed to NOT BE USED WITH A DGPU, need x16 lanes? You want x16 lanes and 8 cores? AMD ALREADY HAS A PRODUCT FOR THAT, the 3600,3700x, etc.... The only people I can see complaining about an APU not having x16 lanes are a scumbags who thought they'd get one over on AMD by picking up one of these APUs for cheaper than a 3700x and pairing it with a dGPU... And I'm sure it'll be the scumbags crying the loudest. What's next? Complaining about a mITX board only having one PCIe slot? "I'm entitled to AMD fulfilling my every desire no matter how unrealistic"

Jeez, whomever wrote this article is doing nothing but being sensational and trying to stoke the fires because other than demonstrating a ridiculous sense of entitlement (the article basically implies that AMD should do everything we want, no matter how ridiculous, or suffer our scorn) I don't understand the goal of this article.

I can't help but think, that if some of these crybabies had put some of this pressure on Intel of Nvidia at least once in the past decade, maybe things would be generally better for the community, but instead when when Intel and Nvidia pull shady stuff, everyone just bends over and asks for seconds.

I'm not trying to defend AMD as much as I'm trying to defend competition... This is a critical time for AMD, they need to capitalize as much as they can and as fast as they can in order to build up a war chest so that thry have the financial power necessary to come back at Intel when Intel INEVITABLY answers back. If AMD is hamstrung now, then the past few years of glorious and beneficial competition could come to an end and we'll find ourselves back in the dystopia before Ryzen launched and if I'm ever forced to buy a stagnated CPU with incremental gains every year for $500, I'll swear off PC altogether.

 

[TheoneandonlyMrK]

Yet again, from the place that proved pciex speeds don't matter so much by testing them.
We get this pciex dramma.

So apparently pciex does matter but only when AMD'S is questionable.
I bet every intel review on here says you don't need pciex4.

 

[Chrispy_]

For what it's worth, a 2080Ti runs at 98% of its peak speed using PCIe 2.0 from 13 years ago.

PCIe 4.0 is about storage, and honestly there's not yet enough on the market to make consumers buying a budget B-series motherboard worry about it. It matters to X570, Z490, and it matters to X399 - and even then, only if the machine in question is going to need multiple PCIe 4.0 SSDs which is extremely unlikely whilst still qualifying as "consumer" workloads.

 

[TheoneandonlyMrK]

For what it's worth, a 2080Ti runs at 98% of its peak speed using PCIe 2.0 from 13 years ago.

PCIe 4.0 is about storage, and honestly there's not yet enough on the market to make consumers buying a budget B-series motherboard worry about it. It matters to X570, Z490, and it matters to X399 - and even then, only if the machine in question is going to need multiple PCIe 4.0 SSDs which is extremely unlikely whilst still qualifying as "consumer" workloads.

Well I am using a vega64 at pciex3x8 like this on an x470 due to nvme drive's on the other lanes , my graphics performance is hardly affected but I don't tend to saturate my Vram so I get no dramma.
I could make some dramma for myself by buying a 5600Xt then trying to game on max settings at 4k like I would if I was a click bait generator.

 

[Chrispy_]

Well I am using a vega64 at pciex3x8 like this on an x470 due to nvme drive's on the other lanes , my graphics performance is hardly affected but I don't tend to saturate my Vram so I get no dramma.
I could make some dramma for myself by buying a 5600Xt then trying to game on max settings at 4k like I would if I was a click bait generator.

Even then with a 5600XT at 4K max settings, you'd struggle to see any difference that couldn't be attributed to margin of error in testing.

 

[Valantar]

The main assumption in this article - that there would be yet-to-be-activated PCIe 4.0 hardware on the Renoir die - is entirely unreasonable. This would be a massive waste of money on AMD's part - after all, the mobile parts here can safely be assumed to outsell desktop APUs by 10-100x. Even a 1% die size increase for a desktop-only feature would then need to result in a significant price premium for the desktop parts in order for it to be worth it in any way. So no, nobody in their right mind has assumed that Renoir had PCIe 4.0 that would be enabled for desktop APUs.

It will nonetheless be interesting to see how Renoir's PCIe lanes are routed for desktop chips given that they in one way have more PCIe than the CPUs. Zen 2 CPUs have one x16 "PCIe graphics" block + one x4 block for storage (of course these designations are rather meaningless; a GPU can run just fine off an m.2 adapter should you want to, and the x16 can be bifurcated and used for storage). Renoir has an x8 PEG block, but two x4 storage blocks (that can either act as 4x SATA or PCIe 3.0 x4). Will it even be possible to utilize all of this on a desktop platform designed around a two-block PCIe lane setup (which AM4 has always had)? Where will the last x4 block be routed to? Are there free pins on the AM4 socket that could be routed to an APU-only m.2 slot on new boards, or some setup where those lanes are otherwise utilized? Or will this x4 block take on the role of the chipset uplink, which seems to be absent from AMD's own Renoir block diagrams?

 

[_Flare]

It was speculated, that IF Renoir would use a fabric based on PCIe4 only between CPU and GPU it could never run on non-PCIe4 mainboards.
This compatibility issue could be also a cause for AMD to not use Navi but Vega.
This decision could indeed hinder the use of PCIe4 for Renoir completely, but thats speculative also.

 

[B-Real]

This was a way to mitigate the missing 8 lines... Bad move.

In terms of what?

 

[AlB80]

There is no difference in control logic between PCIe gen 3 and 4. The difference Is only in frequency (PHY).
AMD has PCIe4 controllers on 12nm (io chiplet) and 7nm (navi), so there is no any reasons to limit Renoir with PCIe3 except TDP.

 

[Valantar]

It was speculated, that IF Renoir would use a fabric based on PCIe4 only between CPU and GPU it could never run on non-PCIe4 mainboards.
This compatibility issue could be also a cause for AMD to not use Navi but Vega.
This decision could indeed hinder the use of PCIe4 for Renoir completely, but thats speculative also.

That makes no sense. Unless those lanes were bifurcated off a single controller (which they aren't), the link speed and generation of the IGP link would have no relation to the same for any other lanes coming off the CPU. Ryzen 3000 on X570 can easily combine PCIe 4.0, 3.0 and even 2.0 or 1.0 for that matter. Absolute worst case scenario the IGP link would step down to 3.0 speeds, though there would be no reason for this to happen.

 

[GoldenX]

In terms of what?

Running a 16x GPU in a physically limited 8x slot? There is a bandwidth penalty for that, and it's very noticeable in emulators.

 

[kapone32]

That makes no sense. Unless those lanes were bifurcated off a single controller (which they aren't), the link speed and generation of the IGP link would have no relation to the same for any other lanes coming off the CPU. Ryzen 3000 on X570 can easily combine PCIe 4.0, 3.0 and even 2.0 or 1.0 for that matter. Absolute worst case scenario the IGP link would step down to 3.0 speeds, though there would be no reason for this to happen.

I have a Sx8200 480GB running on my PCIe 2.0 x4 drive. It doesn't do 3000 mb/s but it does saturate the PCIe bus. That is on a FM2+ board from 2014.

 

[GoldenX]

@theoneandonlymrk care to give a counter-argument? I can provide numbers if you wish.

 

[TheoneandonlyMrK]

@theoneandonlymrk care to give a counter-argument? I can provide numbers if you wish.

If you can't see a niche from a mile away what's the point debating with you.
I wouldn't argue it couldn't be the case any I tried worked ok but I haven't bothered in a while.
But that's a niche not many will have troubles with.

 

[GoldenX]

Nice logic there. "What you do is not 100% the same as me, ergo, your facts are useless".