AMD Files Patent for its Own big.LITTLE Tech - Processor Clusters

[btarunr]

In a sign of AMD's answer to Intel Hybrid tech being quite far away from implementation in a product, the company filed patents to a rival/similar technology only as recently as June 30, 2020, with the patent application being dug up by Underfox. The patent calls for a multi-core processor topology with two kinds of CPU cores - a "high-feature" core (big core), and a "low-feature" one (small core).

Here's where AMD's design is different: it calls for closely integrated groups of the two kinds of cores (one big core, and one small core), called "Processor Clusters." The dedicated L1 caches of the big and small cores in each group shadow data, while an L2 cache is shared between the two cores. Several such big+small Processor Clusters sit across a die, sharing the chip's last-level cache (L3 cache). This is unlike Intel's Hybrid design, where the big and small cores are spread apart on the die, with little cache coherency (Lakefield die-shot by le Comptoir du Hardware below). The patent also details the workflow of how the processor reconciles the ISA differences between the two core types.



View at TechPowerUp Main Site

 

[Xzibit]

What they learned on "Project Skybridge"

 

[InVasMani]

So I guess more trivial tasks will be offloaded, but when higher feature requirements are met it detects it and switches to the more robust higher feature larger chip.

 

[Nephilim666]

Whilst my understanding is rudimentary at best, this seems like a pretty clever way to lower latency when switching from high/low feature cores.

 

[Vya Domus]

I hope we wont see these in desktops, it's not their place.

 

[watzupken]

I hope we wont see these in desktops, it's not their place.

I agree. In the mobile space, this made sense.

 

[ZoneDymo]

I hope we wont see these in desktops, it's not their place.

but of an odd remark, how do you know so well what the future holds and what place this tech does and doesnt have?

 

[Vya Domus]

how do you know so well what the future holds and what place this tech does and doesnt have?

You only need a general idea of what these things are good for, you don't have to know what the future holds. big.LITTLE is an extreme power saving measure that's unneeded in desktops.

 

[Mouth of Sauron]

You only need a general idea of what these things are good for, you don't have to know what the future holds. big.LITTLE is an extreme power saving measure that's unneeded in desktops.

General ideas about CPU designs are basically the only kind I have ...

However, Intel plans to use the same design on desktops. Would there be some advantages if ALL cores worked at the same time, or say both in pair (since it's here described as such), or it's exclusively either/or situation?

Through my general idea, having 2 cores produced to work in two 'flavours' (because we do have frequency lowering and boosts and whatnot for energy efficient already) seems unreasonable. They 'look' like more expensive to design and occupy more place for nothing.

Some core features/space 'look' as needed to be present on all cores, which seems wasteful. Or perhaps yield for small ones is such good and production cheap that it comes to some calculation?

Now, this whole post is because the fact that both Intel/AMD are talking (or even starting production) about this approach - well, I know very little about pricing or advantages of this 'innovation' - only about ARM cores, where it's kinda obvious - or is it, after all?

I would like to know why, that's all - can anyone who understands this write some short Pros/Cons or something. It will be appreciated...

 

[laszlo]

as the trend is going greener it will have a place in desktop also, office pc's +nuc+....

 

[olymind1]

I'm wondering if lets say the weaker 2 or 4 cores c/would be used only for the OS and its or (user installed) backround processes. Or what else thoose slower cores could be used for?

 

[efikkan]

I'm not a fan of the hybrid approach to begin with, particularly because it increases the complexity of OS scheduling and probably microarchitecture specific code in the OS kernel. It also increases the chance of an OS to behave erratically.

But having a big and a little core share L2 cache is a bad idea. This will make the cache less efficient and possibly increase the cache latency. It will also make it harder for the scheduler to predict the performance. I certainly hope a such design (if it is realized at all) is limited to low power laptops and APUs.

I'm wondering if lets say the weaker 2 or 4 cores c/would be used only for the OS and its or (user installed) backround processes. Or what else thoose slower cores could be used for?

Just open task manager and look at all the threads in there, there may be thousands of threads tied to background processes, drivers, services etc.

 

[Vayra86]

You only need a general idea of what these things are good for, you don't have to know what the future holds. big.LITTLE is an extreme power saving measure that's unneeded in desktops.

Depends. There is still a power budget and there is heat/density issue at play. If those fat cats get a chance to cool down a little bit that could benefit the overall performance as well. Also keep in mind that for x86 its really all about the last five percent and even that is being very generous. Steps forward will require out of the box designs.

I still think its an interesting route, and I also think AMD has a better (again) plan when it comes to yields and product stacks. The mess of Intel Alder Lake core configurations... holy crap. This however, looks sensible. It is likely you also want the better small cores with the better big cores and they're still sticking to chiplets this way.

In some way this also reminds of Bulldozer/Piledriver, except now the bottleneck is just the large core perf. So yes, we could think 'why bother' and I get that, part of me does it too. But when you take Intel's bursty CPU management the idea suddenly isn't so strange. And AMD is fast approaching that as well, even if their boost is more intelligent and bases are higher, they still do get warm on a tiny surface area.

 

[InVasMani]

It'll be interesting to see if they can squeeze one of these chips in with the I/O hub to pretty much just add to their current chip designs w/o really sacrificing anything in the process and where a larger chip wouldn't have worked and fit, but a smaller one could. Also it'll be interesting to see how precision boost works in tandem with this.

Depends. There is still a power budget and there is heat/density issue at play. If those fat cats get a chance to cool down a little bit that could benefit the overall performance as well. Also keep in mind that for x86 its really all about the last five percent and even that is being very generous. Steps forward will require out of the box designs.

I still think its an interesting route, and I also think AMD has a better (again) plan when it comes to yields and product stacks. The mess of Intel Alder Lake core configurations... holy crap. This however, looks sensible. It is likely you also want the better small cores with the better big cores and they're still sticking to chiplets this way.

In some way this also reminds of Bulldozer/Piledriver, except now the bottleneck is just the large core perf. So yes, we could think 'why bother' and I get that, part of me does it too. But when you take Intel's bursty CPU management the idea suddenly isn't so strange. And AMD is fast approaching that as well, even if their boost is more intelligent and bases are higher, they still do get warm on a tiny surface area.

Yeah I really see precision boost being something that could come into play with this design. If they can offload certain things to the smaller core and reduce heat in the process they could potentially use it to leverage higher peak boost, longer sustained boost, or higher all core performance and of course mix of all three could be a play. It's a bit like if I can eek out more efficiency well I can eek out more performance. It could also help more than the CPU's themselves potentially like it'll really interesting to see how it impacts motherboards VRM's for example if they aren't over stressed that's a good perk as well and reason enough to consider a bit of this kind of design. I don't see any real negatives to the option of it.

 

[Assimilator]

The mess of Intel Alder Lake core configurations... holy crap. This however, looks sensible.

To me it looks like the most naive way to implement big.LITTLE. To my mind, Alder Lake's design seems more advanced because it apparently allows heterogeneous numbers of big and little cores to be combined, allowing for extreme flexibility (and, yes, potential complexity) - whereas AMD's design always requires a 1:1 big:little core count.

There are already Arm CPUs with 3 different types of cores (small, medium, large as opposed to just big, little) and the heterogeneous core count of Alder Lake makes me strongly suspect it's also designed for this sort of flexibility. Whereas AMD's design doesn't seem much more than, to borrow an old and incorrect analogy, "glue".

 

[Vayra86]

To me it looks like the most naive way to implement big.LITTLE. To my mind, Alder Lake's design seems more advanced because it apparently allows heterogeneous numbers of big and little cores to be combined, allowing for extreme flexibility (and, yes, potential complexity) - whereas AMD's design always requires a 1:1 big:little core count.

There are already Arm CPUs with 3 different types of cores (small, medium, large as opposed to just big, little) and the heterogeneous core count of Alder Lake makes me strongly suspect it's also designed for this sort of flexibility. Whereas AMD's design doesn't seem much more than, to borrow an old and incorrect analogy, "glue".

Yes good arguments as well, but to the glue I respond: 'seems to be working out quite well for AMD'. I'm mostly looking at yields and margins here, not so much flexibility. Its likely we will see a similar trajectory in minor differences as we see now; where Intel has a product for every niche, even the ones nobody knew existed, and AMD has a simple line up top to bottom for a handful of segments.

 

[R0H1T]

I don't see where it's mentioned that a big core needs one small core alongside to work in AMD's implementation of big little. What you're talking about has been in play from ARM as DynamIQ for ages, unless there's a technical limitation to what AMD proposes, in their implementation of clustered cores, it should work the same way! Intel's implementation as of now is useless, a single big core that too neutered to the extent of 7W TDP is just useless in anything but fanless & tablet implementations, even there lower count AMD APUs will beat it to a pulp.

 

[ZoneDymo]

You only need a general idea of what these things are good for, you don't have to know what the future holds. big.LITTLE is an extreme power saving measure that's unneeded in desktops.

Well imagine if offices around hte world adopt this, massive energy saving is a good thing these days.

 

[Vya Domus]

Well imagine if offices around hte world adopt this, massive energy saving is a good thing these days.

big.LITTLE saves a couple of watts, in a phone that matters, in an office PC, I doubt it.

 

[Assimilator]

big.LITTLE saves a couple of watts, in a phone that matters, in an office PC, I doubt it.

In millions of office PCs around the world that are on 24/7/365 because of corporate IT policies?

Yeah, it matters.

 

[Vya Domus]

In millions of office PCs around the world that are on 24/7/365 because of corporate IT policies?

There may be "millions" but the average business needs what, a couple of dozen PCs at the most ? It's not going to matter, they have other things to worry about besides an extra 10$ on an electricity bill, if that.

It's the same logic with "If we all took 1 minute showers we'd save so much water and money". Yeah, maybe we would but to the individual it makes no difference.