- Joined
- Oct 9, 2007
- Messages
- 47,300 (7.53/day)
- Location
- Hyderabad, India
| System Name | RBMK-1000 |
|---|---|
| Processor | AMD Ryzen 7 5700G |
| Motherboard | ASUS ROG Strix B450-E Gaming |
| Cooling | DeepCool Gammax L240 V2 |
| Memory | 2x 8GB G.Skill Sniper X |
| Video Card(s) | Palit GeForce RTX 2080 SUPER GameRock |
| Storage | Western Digital Black NVMe 512GB |
| Display(s) | BenQ 1440p 60 Hz 27-inch |
| Case | Corsair Carbide 100R |
| Audio Device(s) | ASUS SupremeFX S1220A |
| Power Supply | Cooler Master MWE Gold 650W |
| Mouse | ASUS ROG Strix Impact |
| Keyboard | Gamdias Hermes E2 |
| Software | Windows 11 Pro |
At Intel, we truly believe in the potential of technology to enrich lives and change the world. This has been a guiding principle since the company was founded. It started with the PC era, when technology enabled the mass digitization of knowledge and networking, bringing 1 billion people onto the internet. Then came the mobile and cloud era, a disruption that changed the way we live. We now have over 10 billion devices connected to supercomputers in the cloud.
We believe the next era will be the intelligent era. An era where we will experience 100 billion intelligent connected devices. Exascale performance and architecture will make this intelligence available to all, enriching our lives in more ways than we can imagine today. This is a future that inspires and motivates me and my fellow Intel architects every day.
We are generating data at a faster rate than our current ability to analyze, understand, transmit, secure and reconstruct it in real time. Analyzing a ton of data requires a ton of compute. More important, for this data to help us with insights, it needs access to compute in real time, which means low-latency, close to the user. At Intel, we are on a journey to solve this exponentially hard problem.
Since the end of the Dennard scaling era, extracting the exponential value from transistor technology inspired us to look at new approaches across the whole stack. This led us to what we call our Six Pillars of Technology Innovation, which we introduced at our Architecture Day in December 2018. We believe that delivering advances across these pillars is necessary to continue the exponential essence of Moore's Law.
This week, at Architecture Day 2020, we showcased how we are taking this forward with a broad range of exciting new breakthroughs. We have made great progress with our diverse mix of scalar, vector, matrix and spatial architectures - designed with state-of-the-art process technology, fed by disruptive memory hierarchies, integrated into systems with advanced packaging, deployed at hyperscale with lightspeed interconnect links, unified by a single software abstraction, and developed with benchmark defining security features.
We provided more details about our disaggregated design methodology and our advanced packaging roadmap. We demonstrated our mastering of fine bump pitches in EMIB and Foveros technologies through several product iterations in graphics and FPGAs, and on the client with Lakefield.
We also shared one of the most exciting advancements in our transistor roadmap by introducing our new 10 nm SuperFin technology, a redefinition of the FinFET with new SuperMIM capacitors that enables the largest single, intranode enhancement in Intel's history, delivering performance improvements comparable to a full-node transition and enabling a leadership product roadmap.
When we integrate our next-generation Willow Cove CPU architecture with our 10 nm SuperFin technology, the result is the incredible new Tiger Lake platform. We unpacked details of the upcoming Tiger Lake system-on-chip architecture, which provides a generational leap in CPU performance, leadership graphics, leadership artificial intelligence (AI), more memory bandwidth, additional security features, better display, better video and more. I know everyone is eager for all of the details on Tiger Lake and we look forward to sharing more in the coming weeks.
In addition to Tiger Lake, we provided a deep dive into our next generation Intel Agilex FPGA, which provides breakthrough performance per watt. In fact, we showcased two generations of disaggregated products using EMIB and shared the first results of our 224 Gbps transceivers.
We also highlighted how Intel's Xe GPU architecture is the foundation that helps us build GPUs that are scalable from teraflops to petaflops. Xe-LP powers leadership graphics in Tiger Lake and is our most efficient microarchitecture for PC and mobile computing platforms. Xe-LP also powers our first discrete GPU in more than 20 years, codenamed DG1. This GPU is now in production. We also introduced the first Intel server GPU, powered by Xe-LP. This GPU will ship later this year and deliver class-leading stream density and visual quality for media transcode and streaming.
On the data center front, we announced that our first?Xe-HP chip is sampling to customers. Xe-HP is the industry's first multitiled, highly scalable, high-performance GPU architecture, providing petaflop-scale AI performance and rack-level media performance in a single package based on our EMIB technology. Xe-HP will leverage enhanced SuperFin technology.
And, our enthusiast and gamer friends, we heard your requests for Xe for enthusiast gaming. We added a fourth microarchitecture to the Xe family: Xe-HPG optimized for gaming, with many new graphics features including ray tracing support. We expect to ship this microarchitecture in 2021 and I can't wait to get my hands on this GPU!
On software, we have talked before about our vision for providing developers a unified, standards-based programming model across all our XPU architectures. We are executing on that vision with our oneAPI Gold release available later this year. We also announced that we are offering DG1 early access to developers in Intel DevCloud, enabling them start developing with oneAPI without need for any setups, downloads and hardware installs.
Since our last Architecture Day, we have made some big steps in memory. Most recently, as part of the 3rd Gen Intel Xeon Scalable processor launch (code-named "Cooper Lake"), we announced our 2nd Gen Intel Optanepersistent memory product (code-named "Barlow Pass"). We also remain on track to move Intel's 4-bit-per-cell QLC into production by the end of 2020.
We also took a deeper look at how we are advancing security amid a constantly evolving threat landscape. This includes the introduction of new technologies, such Intel Control-Flow Enforcement Technology, which delivers CPU-level security structures to help protect against common malware attack methods. And, we gave the first look at our longer-term vision around foundational security, workload protection and software reliability.
We have made major progress in advancing interconnect, too. Intel announced in March 2019 that it was working with the industry for broad support for Compute Express Link, designed to accelerate next-generation data center performance and to be offered in Sapphire Rapids. We have also had a significant lead with silicon photonics in terms of customer engagements, and as the data center continues its transformation, Intel is addressing their needs through leadership speeds and foundational and SmartNIC products for network processing offloads.
Our Intel fellows and architects are passionately working on technology for 2021, 2022 and beyond. We provided a glimpse into our product vision for client and data center leveraging for all six pillars and disaggregated design. Our head of Intel Labs also provided a look at where emerging research areas can get us 100x to 1000x improvements in compute efficiency, including a sneak peek at neuromorphic architectures being researched in our world-leading labs.
For decades, Intel has been at the center of the technology industry. Our products, along with those of our customers, have reshaped the way we all work, live and play. But our collective journey is far from over. I believe we are at the start of a new era, an intelligent era, an exascale for everyone era. This era will be powered by unprecedented levels of compute performance and disruptions across all Six Pillars of Technology Innovation.
The complete slide deck follows.
View at TechPowerUp Main Site
We believe the next era will be the intelligent era. An era where we will experience 100 billion intelligent connected devices. Exascale performance and architecture will make this intelligence available to all, enriching our lives in more ways than we can imagine today. This is a future that inspires and motivates me and my fellow Intel architects every day.
We are generating data at a faster rate than our current ability to analyze, understand, transmit, secure and reconstruct it in real time. Analyzing a ton of data requires a ton of compute. More important, for this data to help us with insights, it needs access to compute in real time, which means low-latency, close to the user. At Intel, we are on a journey to solve this exponentially hard problem.
Since the end of the Dennard scaling era, extracting the exponential value from transistor technology inspired us to look at new approaches across the whole stack. This led us to what we call our Six Pillars of Technology Innovation, which we introduced at our Architecture Day in December 2018. We believe that delivering advances across these pillars is necessary to continue the exponential essence of Moore's Law.
This week, at Architecture Day 2020, we showcased how we are taking this forward with a broad range of exciting new breakthroughs. We have made great progress with our diverse mix of scalar, vector, matrix and spatial architectures - designed with state-of-the-art process technology, fed by disruptive memory hierarchies, integrated into systems with advanced packaging, deployed at hyperscale with lightspeed interconnect links, unified by a single software abstraction, and developed with benchmark defining security features.
We provided more details about our disaggregated design methodology and our advanced packaging roadmap. We demonstrated our mastering of fine bump pitches in EMIB and Foveros technologies through several product iterations in graphics and FPGAs, and on the client with Lakefield.
We also shared one of the most exciting advancements in our transistor roadmap by introducing our new 10 nm SuperFin technology, a redefinition of the FinFET with new SuperMIM capacitors that enables the largest single, intranode enhancement in Intel's history, delivering performance improvements comparable to a full-node transition and enabling a leadership product roadmap.
When we integrate our next-generation Willow Cove CPU architecture with our 10 nm SuperFin technology, the result is the incredible new Tiger Lake platform. We unpacked details of the upcoming Tiger Lake system-on-chip architecture, which provides a generational leap in CPU performance, leadership graphics, leadership artificial intelligence (AI), more memory bandwidth, additional security features, better display, better video and more. I know everyone is eager for all of the details on Tiger Lake and we look forward to sharing more in the coming weeks.
In addition to Tiger Lake, we provided a deep dive into our next generation Intel Agilex FPGA, which provides breakthrough performance per watt. In fact, we showcased two generations of disaggregated products using EMIB and shared the first results of our 224 Gbps transceivers.
We also highlighted how Intel's Xe GPU architecture is the foundation that helps us build GPUs that are scalable from teraflops to petaflops. Xe-LP powers leadership graphics in Tiger Lake and is our most efficient microarchitecture for PC and mobile computing platforms. Xe-LP also powers our first discrete GPU in more than 20 years, codenamed DG1. This GPU is now in production. We also introduced the first Intel server GPU, powered by Xe-LP. This GPU will ship later this year and deliver class-leading stream density and visual quality for media transcode and streaming.
On the data center front, we announced that our first?Xe-HP chip is sampling to customers. Xe-HP is the industry's first multitiled, highly scalable, high-performance GPU architecture, providing petaflop-scale AI performance and rack-level media performance in a single package based on our EMIB technology. Xe-HP will leverage enhanced SuperFin technology.
And, our enthusiast and gamer friends, we heard your requests for Xe for enthusiast gaming. We added a fourth microarchitecture to the Xe family: Xe-HPG optimized for gaming, with many new graphics features including ray tracing support. We expect to ship this microarchitecture in 2021 and I can't wait to get my hands on this GPU!
On software, we have talked before about our vision for providing developers a unified, standards-based programming model across all our XPU architectures. We are executing on that vision with our oneAPI Gold release available later this year. We also announced that we are offering DG1 early access to developers in Intel DevCloud, enabling them start developing with oneAPI without need for any setups, downloads and hardware installs.
Since our last Architecture Day, we have made some big steps in memory. Most recently, as part of the 3rd Gen Intel Xeon Scalable processor launch (code-named "Cooper Lake"), we announced our 2nd Gen Intel Optanepersistent memory product (code-named "Barlow Pass"). We also remain on track to move Intel's 4-bit-per-cell QLC into production by the end of 2020.
We also took a deeper look at how we are advancing security amid a constantly evolving threat landscape. This includes the introduction of new technologies, such Intel Control-Flow Enforcement Technology, which delivers CPU-level security structures to help protect against common malware attack methods. And, we gave the first look at our longer-term vision around foundational security, workload protection and software reliability.
We have made major progress in advancing interconnect, too. Intel announced in March 2019 that it was working with the industry for broad support for Compute Express Link, designed to accelerate next-generation data center performance and to be offered in Sapphire Rapids. We have also had a significant lead with silicon photonics in terms of customer engagements, and as the data center continues its transformation, Intel is addressing their needs through leadership speeds and foundational and SmartNIC products for network processing offloads.
Our Intel fellows and architects are passionately working on technology for 2021, 2022 and beyond. We provided a glimpse into our product vision for client and data center leveraging for all six pillars and disaggregated design. Our head of Intel Labs also provided a look at where emerging research areas can get us 100x to 1000x improvements in compute efficiency, including a sneak peek at neuromorphic architectures being researched in our world-leading labs.
For decades, Intel has been at the center of the technology industry. Our products, along with those of our customers, have reshaped the way we all work, live and play. But our collective journey is far from over. I believe we are at the start of a new era, an intelligent era, an exascale for everyone era. This era will be powered by unprecedented levels of compute performance and disruptions across all Six Pillars of Technology Innovation.
The complete slide deck follows.
View at TechPowerUp Main Site
.where can i get some rbg for my straight jacket.
