Big little is the future....even AMD is patenting it and probably getting a shot at it.
Perhaps, perhaps not. We have heared things like this before.
I'm not a fan of it, and don't believe it belongs on the desktop, since this puts a tremendous burden on the OS scheduler to manage it well, possibly to the extent where the OS needs a firmware module per CPU microarchitecture like on ARM.
There is also a risk that this will end up only looking well in synthetic benchmarks but induce terrible latency in reality.
Increasing IPC in a core means one thing. That core will get fatter and fatter and fatter and you can gate it and turn it off so muchuntil you hit a wall and that is your lowest wattage.
"Fatter" in terms of transistors, yes, but not necesassarily in terms of die space.
Die sizes:
Sandy Bridge: 18.5 mm²
Skylake: 8.7 mm²
Ice Lake: 6.9 mm²
At the moment, we're hitting a clock speed wall, and will continue to do so until we get wastly different materials. So any architectural improvement which can yield a substantial IPC gain is worth it. As we can see with Intel's 14nm, it remains very energy efficient at ~4 GHz, but gets terribly inefficient at >4.5 GHz. So trading off some max boost clocks for higher IPC is certainly a good idea.
So if AMD or Intel want to double their IPC in the next 5 years (<snip>), they simply have no other choice than go big little if they wanna keep especially power in check.
Perhaps for mobile devices.
But there are substantial improvements coming down the line. Significant IPC gains may also help energy efficiency, at least for demanding threads. Small cores only makes sense for non-demanding threads.
and they need to do it since Apple A14 big core might just have the same IPC as Zen 2 and Skylake
IPC is
Instructions Per Clock,
not performance per clock. Comparing IPC across ISAs is completely pointless. ARM needs more instructions to do the same amount of work, especially compared to advanced x86 instructions which can eliminate a lot of branching logic. A RISC design will never be able to compete with x86 in this way.
And don't forget than AMD Zen 2 core is a relatively modest core in terms of IPC. It is 5-10% better than Skylake which is a core from 2015.
Actually not. Zen 2 wins with heavy multithreaded workloads because Skylake have to throttle due to the inferior node, resulting in Skylake running much lower clocks than advertised for heavy multithreaded workloads.
AMD is adding more and more IPC, Zen 3 will be 20% better, Zen 4 hopefully the same or more. All that extra IPC means more units, more power, so they will be forced to go big little as well, unless they find some other technical idea/solution for this problem.
I certainly hope Zen 3 and Zen 4 will push the performance levels forward, but I don't think it's an established fact that Zen 3 will offer "20%" more performance, and under which conditions.
I don't know what architectural innovations AMD have in store, but apparently Golden Cove (Sapphire Rapids) is "significantly bigger" than Sunny Cove (Ice Lake), and Intel are working on things like "threadlets" and ISA improvements. We are nowhere near a theoretical limit in single core speed, but it's a balancing act. For Haswell and Skylake Intel prioritized SIMD performance and cache bandwidth, benefiting many workloads substantially, while others got minimal gains. Going forward, we should expect both AMD and Intel to create more advanced front-ends, more execution ports with more ALUs and FPU/vector units, etc.
