TSMC Ramps Up 3 nm Node Production

[AleksandarK]

TSMC has had quite a good time recently. They are having all of their capacity fully booked and the development of new semiconductor nodes is going good. Today, thanks to the report of DigiTimes, we have found out that TSMC is ramping up the production lines to prepare for 3 nm high-volume manufacturing. The 3 nm node is expected to enter HVM in 2022, which is not that far away. In the beginning, the new node is going to be manufactured on 55.000 wafers of 300 mm size, and it is expected to reach as much as 100.000 wafers per month output by 2023. With the accelerated purchase of EUV machines, TSMC already has all of the equipment required for the manufacturing of the latest node. We are waiting to see more details on the 3 nm node as we approach its official release.


View at TechPowerUp Main Site

 

[biffzinker]

This 000.3nm isn't actually by definition a true 3nm process before electron quantum tunneling spoils the fun?

 

[Tardian]

Twenty years ago we were using 180 nm. So 3 nm must have something like 3,600 times the density of transistors. The future is scary.

 

[ZoneDymo]

Twenty years ago we were using 180 nm. So 3 nm must have something like 3,600 times the density of transistors. The future is scary.

dont worry, we soon cant go much further

 

[repman244]

dont worry, we soon cant go much further

People keep saying that for the last 20 years as well

 

[Vya Domus]

People keep saying that for the last 20 years as well

They said that for different reasons, there was no clock and power headroom which was correct, the transistor counts were still going up.

 

[fynxer]

Time to move to other materials that is easier to shrink and are more effective, prices is getting way to high per wafer using silicon.

 

[repman244]

They said that for different reasons, there was no clock and power headroom which was correct, the transistor counts were still going up.

Not really, I remember problems associated with wavelengths of lithography that started around 90nm era.

 

[fynxer]

Twenty years ago we were using 180 nm. So 3 nm must have something like 3,600 times the density of transistors. The future is scary.

TSMC 7nm node is i reality 22nm and Intel 14nm is in reality 24nm, measured with microscope.

We are still way off real 3nm so the future aren't that scary yet

 

[Tardian]

https://en.wikipedia.org/wiki/2_nm_process

In late 2018, TSMC chairman Mark Liu predicted chip scaling would continue to 3 nm and 2 nm nodes; however, as of 2019 other semiconductor specialists were undecided as to whether nodes beyond 3 nm could become viable. TSMC began research on 2 nm in 2019. TSMC expected to transition from FinFET to GAAFET transistor types when moving from 3nm to 2nm. It has been reported that TSMC is expected to enter 2 nm risk production around 2023 or 2024. In Aug 2020 TSMC began building a R&D lab for 2nm technology in Hsinchu, expected to become partially operational by 2021. In Sep 2020 (SEMICOM Taiwan 2020) it was reported that TSMC Chairman Mark Liu had stated the company would build a plant for the 2nm node at Hsinchu in Taiwan, and that it could also install production at Taichung dependent on demand.

Intel's 2019 roadmap scheduled potentially equivalent 3nm and 2nm nodes for 2025 and 2027 respectively.

From there the industry moves to Angstrom as a measurement. Moore's Law will probably result in no law ... lawlessness, and trillionaire robber barons who own everything and every one and do whatever they like.

 

[R0H1T]

This 000.3nm isn't actually by definition a true 3nm process before electron quantum tunneling spoils the fun?

Who cares, so long as TSMC is beating Intel at the foundry game it really doesn't matter if they name it 3nm or 3pm & given the lead Intel 14nm+++ still has supposedly over TSMC 7nm isn't it incredible that AMD's beating Intel so handsomely with an inferior node

Intel 14 nm Node Compared to TSMC's 7 nm Node Using Scanning Electron Microscope

 

[RH92]

TSMC 7nm node is i reality 22nm and Intel 14nm is in reality 24nm, measured with microscope.

We are still way off real 3nm so the future aren't that scary yet

This ! Those numbers are nothing more than marketing fuss , real transistor size in those nodes is much bigger so we are not hitting the quantum tunneling wall anytime soon ( at least not for the next 10-20 years ) .

 

[Mescalamba]

I assume you can always try to divide microprocessors into many and make up with quantity when size becomes problem (eg. when it cant get smaller).

Also 3D chips, unsure if thats possible?

 

[bonehead123]

3nm is sooooo 2019, gimme some of dat yactometer-sized stuff already, like, yesterday...hahahaha ......

Oh and btw, GO TSMC !!!!!!!

 

[Steevo]

We are reaching atomic scale transistors. Next up will probably be 3D stacked printing as we cannot avoid quantum effect, or we will start using quantum effect for the transistors.

 

[MxPhenom 216]

This ! Those numbers are nothing more than marketing fuss , real transistor size in those nodes is much bigger so we are not hitting the quantum tunneling wall anytime soon ( at least not for the next 10-20 years ) .

That actually depends. If you were to check the length and width of every transistor in a chip fabricated at some node there would be a good chunk of them that would actually be those sizes but not all of them. Then there is transistor sizing during the PnR/layout stage which is an optimization done for timing and propagation delay.

Fabs give chip designers a library of cells and these cells usually are distinguished by their drive strength (size) and how much leakage that cell has.

 

[medi01]

Just a reminder on transistot sizes

Intel 14nm is 24nm by 24nm
TSMC 7nm is 22nm by 22nm

Curious eh?

 

[Tardian]

See: https://www.techpowerup.com/272489/...ng-scanning-electron-microscope?cp=2#comments

Look for comment #41 made by RandallFlagg.

Transistor Gate Pitch seems not entirely related to the nm lithography process. What appears to be the new standard is Transistor density (MTr/mm^2).

The above table copied from the abovementioned post. I also recommend the following:

7 nm lithography process - WikiChip

The 7 nanometer (7 nm) lithography process is a technology node semiconductor manufacturing process following the 10 nm process node. Mass production of integrated circuit fabricated using a 7 nm process began in 2018. The process technology will be phased out by leading-edge foundries by...

en.wikichip.org

 

[TheoneandonlyMrK]

Not really, I remember problems associated with wavelengths of lithography that started around 90nm era.

EUV just pressed the reset button on all wavelength issues, and we have 10-15 years before we reach next generation materials point but then, competition breads innovation so who knows.