Samsung Demonstrates 256 Gb 3 nm MBCFET Chip at ISSCC 2021

[AleksandarK]

During the IEEE International Solid-State Circuits Conference (ISSCC), Samsung Foundry has presented a new step towards smaller and more efficient nodes. The new chip that was presented is a 256 Gb memory chip, based on SRAM technology. However, all of that doesn't sound interesting, until we mention the technology that is behind it. Samsung has for the first time manufactured a chip using the company's gate-all-around field-effect transistor (GAAFET) technology on the 3 nm semiconductor node. Formally, there are two types of GAAFET technology: the regular GAAFET that uses nanowires as fins of the transistor, and MBCFET (multi-bridge channel FET) that uses thicker fins that come in a form of a nanosheet.

Samsung has demonstrated the first SRAM chip that uses MBCFET technology today. The chip in question is a 256 Gb chip with an area of 56 mm². The achievement Samsung is proud of is that the chip uses 230 mV less power for writes, compared to the standard approach, as the MBCFET transistors allow the company to have many different power-saving techniques. The new 3 nm MBCFET process is expected to get into high-volume production sometime in 2022, however, we are yet to see demos of logic chips besides SRAM like we see today. Nonetheless, even the demonstration of SRAM is big progress, and we are eager to see what the company manages to build with the new technology.


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[TumbleGeorge]

For what purpose? 32GB L1 cache?

 

[Tom Yum]

For what purpose? 32GB L1 cache?

SRAM is frequently what fabs use to demonstrate new nodes under development because a SRAM cell is extremely simple to fabricate (comparatively). Having said that, 32GB of L1 would be epic, wouldn't need to buy memory at least!

 

[Raiju]

More like a L4 cache as seen in the Intel 5775c as it requires a separate package.

 

[Wirko]

That's 256 megabits, not 256 gigabits. The latter would amount to 27000 Mtr/mm². We're not there yet, we're at one hundredth of that.

 

[TumbleGeorge]

That's 256 megabits, not 256 gigabits. The latter would amount to 27000 Mtr/mm². We're not there yet, we're at one hundredth of that.

Hmm in article is written 256 Gb= 32GB?

More like a L4 cache as seen in the Intel 5775c as it requires a separate package.

View attachment 192070

Mmm eDRAM≠SRAM? Or I'm wrong?

 

[Valantar]

As @Tom Yum said above, this isn't a commercial chip, just a proof of concept/proof of capability for the fab. They're showing that they can fabricate functional and relatively error-free chips at a decent size on a new node with a new transistor shape. Another reason for the use of SRAM chips for this is that the design process is simple, involving far more copy+paste than most chip designs that require complex tuning, tracing of interconnetcts, latency optimizations, etc.

This mainly demonstrates that Samsung is well on the way to implementing 3nm MBCFET for actual products, though I'd be surprised if anything started volume production in less than a year.

 

[Dammeron]

So, the 3nm - what size is it really? 12-15nm?

 

[Valantar]

So, the 3nm - what size is it really? 12-15nm?

Depends what feature size you're looking at. What 3nm tells us is that it's smaller/denser/faster/lower power than 5nm, which again was the same compared to 7nm, etc.. Unless you're doing low-level silicon chip design, the relation between node naming and physical feature size really shouldn't matter to you.

 

[Wirko]

So, the 3nm - what size is it really? 12-15nm?

Calculated from data available at Semiwiki:

Samsung 3nm GAA has 216.37 MTr/mm², so the total size of a single transistor could be something like 68×68 nm, on average. Big, hah?
And the SRAM cell size (6 transistors) is 0.0187 µm², so like 136×136 nm.

Transistor size varies A LOT between different structures, and while logic shrinks very well with each new node, SRAM shrinks quite poorly. For those interested, there's an excellent discussion about that on Real World Tech: Transistor Count - A Flawed Metric

The purpose of this first chip (not just one, my guess is it was a small batch of wafers) is characteriation, anyway. Samsung needs to know exactly what they have produced using mass-manufacturing tools. They need to determine the electrical characteristics of the new transistors and how much they vary within a chip, a wafer, and a batch. The result is a large bunch of data and graphs, like those presented here, that to chip designers mean everything.

 

[DeathtoGnomes]

230MV drop is kinda nice. Wont be long til we are seeing single digit wattage.

 

[RH92]

If im not mistaken TSMC 3nm is going to be based on FinFET technology , it will be interesting to see how it will compare to Samsungs 3nm MBCFET !

 

[Valantar]

If im not mistaken TSMC 3nm is going to be based on FinFET technology , it will be interesting to see how it will compare to Samsungs 3nm MBCFET !

Yeah, that'll be interesting! I wonder if that's enough for Samsung to catch up with TSMC's overall performance and efficiency lead.

 

[Wirko]

Yeah, that'll be interesting! I wonder if that's enough for Samsung to catch up with TSMC's overall performance and efficiency lead.

But cost! That's something we enthusiasts often forget. Samsung needs to keep their own costs and their selling prices reasonable. Those nice multi-level bridges look like they need many additional processing steps, costing money and time.

 

[RH92]

Samsung needs to keep their own costs and their selling prices reasonable. Those nice multi-level bridges look like they need many additional processing steps, costing money and time.

To my understanding this is not true at all especially when comparing MBCFET to FinFET .

In the case of FinFET in order to increase speed you need to place multiple Fins next to each other which takes space horizontally ( which most of the time is not possible ) furthermore this is where double , triple or quadruple patterning ( depending the lithography envolved ) comes to play and this is what is referred to as '' additional processing steps " which adds cost .

On the other hand in the case of MBCFET the Nanosheets ( which replace the fins ) can be stacked vertically , so speed can be increased without any compromise being made to the footprint . Furthermore those Nanosheets are much larger than Fins which should minimise the need for multi-patterning if not eliminate it and thus driving complexity and cost down .

https://www.tomshardware.fr/content/uploads/sites/3/2019/05/mbcfet-samsung.jpg

 

[Wirko]

To my understanding this is not true at all especially when comparing MBCFET to FinFET .

In the case of FinFET in order to increase speed you need to place multiple Fins next to each other which takes space horizontally ( which most of the time is not possible ) furthermore this is where double , triple or quadruple patterning ( depending the lithography envolved ) comes to play and this is what is referred to as '' additional processing steps " which adds cost .

On the other hand in the case of MBCFET the Nanosheets ( which replace the fins ) can be stacked vertically , so speed can be increased without any compromise being made to the footprint . Furthermore those Nanosheets are much larger than Fins which should minimise the need for multi-patterning if not eliminate it and thus driving complexity and cost down .

https://www.tomshardware.fr/content/uploads/sites/3/2019/05/mbcfet-samsung.jpg

I assumed that the stacked structure of MBCFETs requires building each semiconductor layer and each insulating layer separately, by deposition/lithography/etching. That's not the case, as this article explains. However, the procedure needed to process several layers, and spaces between those layers, at once, is exceedingly complex, more than I could imagine when I wrote my previous post.
Reduced complexity and cost are nowhere in sight here. Rather, there are no other options for the foreseeable future.