DDR5-6400 RAM Benchmarked on Intel Alder Lake Platform, Shows Major Improvement Over DDR4

[londiste]

They found some DDR4-3200 MHz CL22??? You can bet your arse that they totally mangled the rest of the DDR4 memory sub-timings to be as high in latency as possible.

JEDEC spec is CL20 to CL22.
DDR5 like other new generation memory standards are likely to get to servers first and there memory tends to be run at standard speeds.

Even when using two DDR5 sticks the system will still be dual channel (dual rank, 2 dimm's per channel) because that is determined by the motherboard. The fact that DDR5 enables dual channel from a single stick does not make the system magickly quad channel when using two or even four sticks. Quad channel requires motherboard and CPU support. Alder Lake-S is dual channel. That more than anything confirms that it will be dual channel.

It does make it dual channel but if each channel is now 32-bit instead of 64-bit as with DDR4 the extra channel benefit is largely negated.

 

[hat]

We go through this every time. Brand new DDR5 will not be as fast as high end DDR4. It will catch up.

 

[vinnyerrero]

"proceeded to compare these results with DDR4-3200 MHz CL22"

what kind of garbage DDR4 comes with such a crappy CL for that speed? CL16 is pretty much the norm for that speed on good memory kits.

CL22 is the JEDEC standard for DDR4-3200.
DDR4 3200 CL16 is an overclocked memory preset

 

[Blaazen]

@ They found some DDR4-3200 MHz CL22?

This is common config of ECC modules. And they are 1,2V (since 1,35 is overclocking).

Micron 32GB DDR4-3200 ECC UDIMM 2Rx8 CL22 | MTA18ASF4G72AZ-3G2B1 | Crucial.com

Buy Micron 32GB DDR4-3200 ECC UDIMM 2Rx8 CL22 MTA18ASF4G72AZ-3G2B1. FREE US Delivery, guaranteed 100% compatibility when ordering using our online tools.

www.crucial.com

 

[Punkenjoy]

Even when using two DDR5 sticks the system will still be dual channel (dual rank, 2 dimm's per channel) because that is determined by the motherboard. The fact that DDR5 enables dual channel from a single stick does not make the system magickly quad channel when using two or even four sticks. Quad channel requires motherboard and CPU support. Alder Lake-S is dual channel. That more than anything confirms that it will be dual channel.

i think you are totally miss the point and also make assumption on things you don't know or understand.

Instruct yourself with this and get back after that:

https://www.micron.com/-/media/client/global/documents/products/white-paper/ddr5_more_than_a_generational_update_wp.pdf?la=en

Protocol Features for Performance In addition to higher data rates and improvements to the I/O circuitry, DDR5 introduces other new protocol features unrelated to data rate that are integral to increasing bandwidth and performance. For example, DDR5 DIMMs feature two 40-bit (32 bits plus ECC) independent channels. When combined with a new default burst length of 16 (BL16) in the DDR5 component, this allows a single burst to access 64B of data (the typical CPU cache line size) using only one of the independent channels, or only half of the DIMM. Providing this ability to interleave accesses from these two independent channels enables tremendous improvements to concurrency, essentially turning an 8-channel system as we know it today into a 16-channel system.

 

[madness777]

Am I the only one that sees the 800MHz CPU clock?
How do you expect memory to perform with 800MHz CPU clock?
This benchmark if more of a ''Oh hey look DDR5 exists'' rather than a valid performance metric. It's incredibly early for DDR5

 

[Tomorrow]

i think you are totally miss the point and also make assumption on things you don't know or understand.

Instruct yourself with this and get back after that:

https://www.micron.com/-/media/client/global/documents/products/white-paper/ddr5_more_than_a_generational_update_wp.pdf?la=en

Nowhere in that PDF does Micron say that regular dual channel systems can now be counted as having quad channel. Yes they talk about benefits of the new design but if you read my posts you will see that i never mentioned that DDR5's two channels per DIMM wont have an advantage. This will be especially useful on OEM systems that currently cheap out and equip systems with a single stick thus incurring a performance penalty.

And users are still wrong when referencing DDR4 as somehow having quad channel by using 4 sticks instead of two on mainstream platforms (not X299 or TR). That needs to be pointed out.

Am I the only one that sees the 800MHz CPU clock?
How do you expect memory to perform with 800MHz CPU clock?
This benchmark if more of a ''Oh hey look DDR5 exists'' rather than a valid performance metric. It's incredibly early for DDR5

Why would that matter? That 800Mhz would affect system performance not memory performance. Unless the IMC was somehow downlocked or something...

 

[bxcounter]

Am I the only one that sees the 800MHz CPU clock?
How do you expect memory to perform with 800MHz CPU clock?
This benchmark if more of a ''Oh hey look DDR5 exists'' rather than a valid performance metric. It's incredibly early for DDR5

Yep, i'm kinda blind today...good catch
That 800Mhz clock explains everything now = bandwith/memory latency/cache latency
Which means cache frequency was also 800 or lower.

 

[TumbleGeorge]

LoL DDR5 is just scrap release at beginning! Cut out a beautiful wide 64 bit channel to pair of old, narrow "rusty" pipes and is it expected that these narrow pipes with a small cross-section will pass a higher flow rate? This is regress, not progress! Why have technologies lately instead of evolving towards improvement .. actually degraded? Are today's scientists and engineers so incompetent? Apparently the time has come and the baton has been taken over by the failed generation, which was born after the end of the Cold War and is made of bad material!

 

[Punkenjoy]

Nowhere in that PDF does Micron say that regular dual channel systems can now be counted as having quad channel. Yes they talk about benefits of the new design but if you read my posts you will see that i never mentioned that DDR5's two channels per DIMM wont have an advantage. This will be especially useful on OEM systems that currently cheap out and equip systems with a single stick thus incurring a performance penalty.

And users are still wrong when referencing DDR4 as somehow having quad channel by using 4 sticks instead of two on mainstream platforms (not X299 or TR). That needs to be pointed out.


Why would that matter? That 800Mhz would affect system performance not memory performance. Unless the IMC was somehow downlocked or something...

I quoted it in my lass message, but i will quote it again for your own benefits :
Page 4 of 6

Protocol Features for Performance In addition to higher data rates and improvements to the I/O circuitry, DDR5 introduces other new protocol features unrelated to data rate that are integral to increasing bandwidth and performance. For example, DDR5 DIMMs feature two 40-bit (32 bits plus ECC) independent channels. When combined with a new default burst length of 16 (BL16) in the DDR5 component, this allows a single burst to access 64B of data (the typical CPU cache line size) using only one of the independent channels, or only half of the DIMM. Providing this ability to interleave accesses from these two independent channels enables tremendous improvements to concurrency, essentially turning an 8-channel system as we know it today into a 16-channel system.

The example is for server. So a server that have a motherboard layout for 8 channel, they will be able to keep a similar layout but this time, they will be able to support 16 channel with the same amount of trace and pin.

A motherboard that is routed for dual channel right now, so by example 2 channel of 2 dimm slot, 1 channel per 288 pin, will have 4 channel with DDR5. The 2 288 pin/trace will still lead to 2 DIMM slot, but they will give 2x32 Channel per 288 pin/trace instead of 1x64.

And a schema from that document explain it well

 

[bxcounter]

Did a quick test to see how much of a difference low CPU/Cache clock makes on DDR4 4100 17-17-17-36 1T.
1=9900k 5.0/4.6 / HT OFF
2=9900k 0.8/0.8 / HT OFF

 

[Punkenjoy]

LoL DDR5 is just scrap release at beginning! Cut out a beautiful wide 64 bit channel to pair of old, narrow "rusty" pipes and is it expected that these narrow pipes with a small cross-section will pass a higher flow rate? This is regress, not progress! Why have technologies lately instead of evolving towards improvement .. actually degraded? Are today's scientists and engineers so incompetent? Apparently the time has come and the baton has been taken over by the failed generation, which was born after the end of the Cold War and is made of bad material!

you mean when we removed beautiful ATA 133 wide channel to replace with a narrow, rusty pipe of Serial ATA ?
Same Deal with PCI vs PCI-E. There are reason for this.

The wider the bus, the harder it is to move data across over long distance at higher frequency. This is why everyone is looking at smaller serial bus that run much faster.

But as a comparaison, DDR5 6400 will be able to send the same 64B line to the CPU in the same exact amount of time it would take a DDR4-3200 DIMM to do. The only difference it will only use half the dimm to do it. The other channel on the DIMM will be free do to other useful work.

 

[Tomorrow]

I quoted it in my lass message, but i will quote it again for your own benefits :
Page 4 of 6


The example is for server. So a server that have a motherboard layout for 8 channel, they will be able to keep a similar layout but this time, they will be able to support 16 channel with the same amount of trace and pin.

A motherboard that is routed for dual channel right now, so by example 2 channel of 2 dimm slot, 1 channel per 288 pin, will have 4 channel with DDR5. The 2 288 pin/trace will still lead to 2 DIMM slot, but they will give 2x32 Channel per 288 pin/trace instead of 1x64.

And a schema from that document explain it well

View attachment 192837

Micron saying something does not make it so. I guess we will see when Alder Lake launches but im pretty sure they wont market it as a quad channel system like HEDT.

 

[Makaveli]

"proceeded to compare these results with DDR4-3200 MHz CL22"

what kind of garbage DDR4 comes with such a crappy CL for that speed? CL16 is pretty much the norm for that speed on good memory kits.

I believe that was done because they are comparing at JEDEC specification.

lol everyone posting what is this crap my DDR4 numbers are better than this.

This is par the course it happends at every new memory generation. DDR5 will eventually give better performance but that will take time not at launch.

 

[Punkenjoy]

Micron saying something does not make it so. I guess we will see when Alder Lake launches but im pretty sure they wont market it as a quad channel system like HEDT.

What Micron say is just explaining what is the JEDEC standard...

The Micron whitepaper explain it well in simple word but if you want a more reliable source, this is on the JEDEC web site:

JEDEC Publishes New DDR5 Standard for Advancing Next-Generation High Performance Computing Systems | JEDEC

www.jedec.org

DDR5 was designed to meet increasing needs for efficient performance in a wide range of applications including client systems and high-performance servers. DDR5 incorporates memory technology that leverages and extends industry know-how and experience developing previous DDR memories. The standard is architected to enable scaling memory performance without degrading channel efficiency at higher speeds, which has been achieved by doubling the burst-length to BL16 and bank-count to 32 from 16. This revolutionary architecture provides better channel efficiency and higher application level performance that will enable the continued evolution of next-generation computing systems. In addition, the DDR5 DIMM has two 40-bit fully independent sub-channels on the same module for efficiency and improved reliability.

All DDR5 DIMM that respect the JEDEC standard will have 2 channel on them (where DDR4 and bellow DIMM only have 1 channel).

 

[Dave65]

is that latency going to be ok for gaming though??? i feel like this is great for synthetics but not great for gaming

Thinking same.

 

[Punkenjoy]

Thinking same.

Latency will depend of what timming these ram have. If they double frequency and double the memory settings (just to make it easy to follow) final latency should be the same.

But there are design change in DDR5 that will improve that actually might not appear in syntethic benchmark. By having 2 memory channel per dimm for a total of 4, you have more memory channel per core. This can mean you can spread your memory read and write to many controller. This make them more available reducing the real latency but maybe not the synthetic one.

Also, unlike DDR4, DDR5 will refresh it's bank on a per bank basis instead of the whole bank group. DRAM still need refreshing and while the memory controller does it, the bank group is unavailable. With DDR5, the rest of the memory will still be able to accomplish some work, reducing again the overall latency but that might not change much the synthetic one

Micron state that at equal spec (So DDR4 3200 vs DDR5-3200), the DDR5 module should be 1.36 time more performant due to all the change they made.

DDR5 is actually a big overhaul of the DDR standard where most of the previous DDR iteration were minor change mixed with doubling the data rate.

 

[TheinsanegamerN]

I couldnt care less if its 64 bit or 2x32 bit or 64x1 bit channels. The total bits per DIMM is still 64, two sticks will still give a 128 bit memory bus. Cool. Now give us those GHz.

 

[TumbleGeorge]

I couldnt care less if its 64 bit or 2x32 bit or 64x1 bit channels. The total bits per DIMM is still 64, two sticks will still give a 128 bit memory bus. Cool. Now give us those GHz.

Dividing kill efficiency? One 64 bit channel is more effective than 2X32 bit? Also is problem in all computer achitectures. More cores in CPU results that in one multi core, a multi thread performance is below of performance of same number individual CPU's with one core each. Same is with water: narrow pipes have more hydraulic losses.

 

[voltage]

cant come soon enough. and, its about time! most people forget DDR5/platforms was originally scheduled to be released in late 2017. socket 1700 + DDR5 please.

 

[Wirko]

What Micron say is just explaining what is the JEDEC standard...

The Micron whitepaper explain it well in simple word but if you want a more reliable source, this is on the JEDEC web site:

JEDEC Publishes New DDR5 Standard for Advancing Next-Generation High Performance Computing Systems | JEDEC

www.jedec.org

All DDR5 DIMM that respect the JEDEC standard will have 2 channel on them (where DDR4 and bellow DIMM only have 1 channel).

You're probably right, you just didn't explain it all that well.

Alder Lake needs to have four memory channels because that's the only way it can transfer data over a 128-bit bus to and from RAM. With only two channels, only 64-bit transfers would be possible, cutting the bandwidth in half compared to dual channel DDR4 at same speed rating. Intel can't afford to cut bandwidth in half overnight.

That said, it's quite possible that there will be no more than two independent channels on the IMC, each with its own buffers, queues, reorder logic, possibly some cache and whatnot. Each of these channels will control data flow over two 32-bit buses ("sub-channels"), with same access pattern on both. The whole thing amounts to two channels by 64 bits each and Intel won't even try to sell it as four-channel. They may still introduce an IMC with four independent channels at a later time and market it as such. "A later time" = the other generation on LGA 1700.

Now I've started wondering what the purported "12-channel DDR5" means in AMD Genoa's case. 12 x 32-bit would be a heavy regression from 8 x 64-bit on Zen 3. So 24 channels but only 12 independent channels, hmm?

 

[Punkenjoy]

You're probably right, you just didn't explain it all that well.

Alder Lake needs to have four memory channels because that's the only way it can transfer data over a 128-bit bus to and from RAM. With only two channels, only 64-bit transfers would be possible, cutting the bandwidth in half compared to dual channel DDR4 at same speed rating. Intel can't afford to cut bandwidth in half overnight.

That said, it's quite possible that there will be no more than two independent channels on the IMC, each with its own buffers, queues, reorder logic, possibly some cache and whatnot. Each of these channels will control data flow over two 32-bit buses ("sub-channels"), with same access pattern on both. The whole thing amounts to two channels by 64 bits each and Intel won't even try to sell it as four-channel. They may still introduce an IMC with four independent channels at a later time and market it as such. "A later time" = the other generation on LGA 1700.

Now I've started wondering what the purported "12-channel DDR5" means in AMD Genoa's case. 12 x 32-bit would be a heavy regression from 8 x 64-bit on Zen 3. So 24 channels but only 12 independent channels, hmm?

The 2 memory channel or subchannel will be totally independent. The only thing that link them is the DIMM voltage controller (that will be on DIMM instead of on the motherboard) and they will be on the same physical DIMM.

Except that both channel will have their own command pin and will need to be managed independently by the memory controller. It is not like the memory controller of GPU.

This give way more flexibility on the memory controller chips as it's easier to fit 4 block of 32 bit memory controller than 2 64 bit block.

On the motherboard. Except the voltage controller. There won't be many change and there will be 2 memory domain like the current situation. The trace on the motherboard are also way easier to trace since you only need to katch

For Genoa. AMD will have up to 12 Chiplets per chips. If they respect the memory configuration of the previous EPYC cpu, it would make sense they go with 12 independ physical domain or DIMM channel with 24 subchannel.

 

[Minus Infinity]

People have short memories, when DDR4 first arrived on the scene it too seemed garbage compared to DDR3 with much worse latencies. We had CAS9 DDR3 and all of a sudden DDR4 appears with CAS22+. Yet look where we are now. Just don't be foolish enough to be an early adopter if it's crap, no one will force you buy DDR5.

 

[Wirko]

The 2 memory channel or subchannel will be totally independent. The only thing that link them is the DIMM voltage controller (that will be on DIMM instead of on the motherboard) and they will be on the same physical DIMM.

Except that both channel will have their own command pin and will need to be managed independently by the memory controller. It is not like the memory controller of GPU.

This give way more flexibility on the memory controller chips as it's easier to fit 4 block of 32 bit memory controller than 2 64 bit block.

On the motherboard. Except the voltage controller. There won't be many change and there will be 2 memory domain like the current situation. The trace on the motherboard are also way easier to trace since you only need to katch

For Genoa. AMD will have up to 12 Chiplets per chips. If they respect the memory configuration of the previous EPYC cpu, it would make sense they go with 12 independ physical domain or DIMM channel with 24 subchannel.

More flexibility comes with more complexity. There's a lot of logic needed per channel - logic that queues and prioritizes read/write requests, sends commands to DIMM, tracks status of individual ranks, manages timing and so on. There's a good overview of what's inside a (single-channel) controller here.

The controller can be made simpler if only two channels are independent. The other two just follow the first two, doubling the bandwidth. For large transfers, you get the full bandwidth of a 128-bit bus. But if four threads request data from four different memory locations, only two requests can be processed at a time. It's a tradeoff, and maybe Intel decides it's good enough for Alder Lake's cores.

Phenoms X4 even had a BIOS option to select ganged mode (two DDR2 channels working as one, or 1 x 128 bit) or unganged mode (two independent DDR2 channels, 2 x 64 bit). In benchmarks, unganged was faster in games and equally fast in everything else.

 

[THU31]

Weird results. The DDR5 stick is obviously running at 4800 MT/s, which would offer a max theoretical bandwidth of 38400 MB/s, so 35844 MB/s would seem right here.

The DDR4 stick cannot be running at 3200 MT/s, as the max theoretical bandwidth at that speed is 25600 GB/s. Actual benchmark results are always a few GB/s slower.

Latency is always really bad in the beginning, so it is not even worth looking at that.

I hope new CPUs and boards will support both standards for a few years. If you have fast XMP DDR4 memory, there is zero point in replacing it with JEDEC-spec DDR5.