AMD's Next-Generation Van Gogh APU Shows Up with Quad-Channel DDR5 Memory Support

[AleksandarK]

AMD is slowly preparing to launch its next-generation client-oriented accelerated processing unit (APU), which is AMD's way of denoting a CPU+GPU combination. The future design is codenamed after Van Gogh, showing AMD's continuous use of historic names for their products. The APU is believed to be a design similar to the one found in the SoC of the latest PlayStation 5 and Xbox Series X/S consoles. That means that there are Zen 2 cores present along with the latest RDNA 2 graphics, side by side in the same processor. Today, one of AMD's engineers posted a boot log of the quad-core Van Gogh APU engineering sample, showing some very interesting information.

The boot log contains information about the memory type used in the APU. In the logs, we see a part that says "[drm] RAM width 256bits DDR5", which means that the APU has an interface for the DDR5 memory and it is 256-bit wide, which represents a quad-channel memory configuration. Such a wide memory bus is typically used for applications that need lots of bandwidth. Given that Van Gogh uses RDNA 2 graphics, the company needs a sufficient memory bandwidth to keep the GPU from starving for data. While we don't have much more information about it, we can expect to hear greater details soon.


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[DeathtoGnomes]

While we don't have much more information about it, we can expect to hear more soon.

More now is better don't ya think?

 

[ixi]

More now is better don't ya think?

Zen 2 cores??? So you wanna tell me. This will be slower than 4xxxG? RDNA2 in apu C_____C?!?

 

[Lord_Soth]

Zen 2 cores??? So you wanna tell me. This will be slower than 4xxxG? RDNA2 in apu C_____C?!?

4000U/H/G apu ARE Zen 2 cores

 

[ixi]

4000U/H/G apu ARE Zen 2 cores

O boy, o boy, you're right. Which means there should be almost none to little IPC improvement. At least RDNA 2 would be nice. Maybe will be capable of full hd 60fps on big titles with medium/high settings?

 

[Lord_Soth]

O boy, o boy, you're right. Which means there should be almost none to little IPC improvement. At least RDNA 2 would be nice. Maybe will be capable of full hd 60fps on big titles with medium/high settings?

Your are right about the step back on cpu side because today 5000g apu are Zen 3 but on gpu side RDNA2 cores with ddr5 and 256 bit bus will be a huge jump in performance from my VEGA 11 ddr4 128 bit .

 

[TumbleGeorge]

I wanna AMD to launch all models Cezanne desktop and all ZEN3 CPU's this month and to be on fast track for Van Gogh! There is problem because has not any information for first AM5 based chipsets and motherboards with it. Independently of old ZEN2 architecture of CPU part Van Gogh must be AM5 because has not AM4 MBs with DDR5 slots. What is precise timing for release of Van Gogh?

 

[ncrs]

Quad-channel DDR5 is equivalent to Dual-channel DDR4 since DDR5 is 32-bit data (+8-bit ECC if present) with 2 channels per DIMM while DDR4 is 64-bit data (+8-bit ECC) with 1 channel per DIMM. So this might mean that it's just a typical 2 or 4 DIMM slot design.

Edit: Actually while the above is correct, it still doesn't explain the 256-bit interface reported by the kernel. That might suggest a 4 DIMM design. How do we call this in DDR5? Quad-? Octo-channel? This is going to get confusing

 

[Post Nut Clairvoyance]

Quad-channel DDR5 is equivalent to Dual-channel DDR4 since DDR5 is 32-bit data (+8-bit ECC if present) with 2 channels per DIMM while DDR4 is 64-bit data (+8-bit ECC) with 1 channel per DIMM. So this might mean that it's just a typical 2 or 4 DIMM slot design.

I was just wondering about how D5 DIMM works out with 256bit.
still, given D5 6400, thats still about 80GB/s, and D5 8400 at just over 100GB/s, that's tailing 1050Ti bandwidth, which is a nice improvement for budget gaming all depending on price. just like when Vega iGPU first came out. Now they are getting a bit slow for anything above esport.
That and current GPU situation -_-; hope Intel pulls out something nice too with their D5 CPUs because I have no idea how much these APUs are gonna cost...

 

[Dredi]

Quad-channel DDR5 is equivalent to Dual-channel DDR4 since DDR5 is 32-bit data (+8-bit ECC if present) with 2 channels per DIMM while DDR4 is 64-bit data (+8-bit ECC) with 1 channel per DIMM. So this might mean that it's just a typical 2 or 4 DIMM slot design.

Edit: Actually while the above is correct, it still doesn't explain the 256-bit interface reported by the kernel. That might suggest a 4 DIMM design. How do we call this in DDR5? Quad-? Octo-channel? This is going to get confusing

It’s more likely that the displayed interface width is calculated from the number of channels and for whatever reason assumes certain width per channel. It wouldn’t make much sense to do a 256bit bus on such a tiny chips.

 

[ncrs]

It’s more likely that the displayed interface width is calculated from the number of channels and for whatever reason assumes certain width per channel. It wouldn’t make much sense to do a 256bit bus on such a tiny chips.

Perhaps, it's early code most likely.

But the interesting question is how do we call 1 DIMM of DDR5? It is technically dual-channel, but historically we've been calling 2 DIMMs that. How many channels will mainstream IMCs have? 4?

 

[AnarchoPrimitiv]

If I remember correctly, AMD is also making APUs with Zen3 and RDNA2, though they're called by a different codename. Regardless, Zen2 cores will be more than fine to max out the graphical capabilities of the RDNA2 CUs in these APUs, so I don't know what everyone is whining about... People aren't going to team one of these van gogh APUs with a top of the line GPU, so Zen3 cores aren't necessary, besides Zen2 cores will keep the price down considerably so these should be ending up in some pretty graphically capable machines (mobile and desktop) at an affordable price.... If these can 1080p at 60fps on high settings for $700 in a laptop or less, they'll sell fast.... And like I said, AMD will be releasing a Zen3/RDNA2 APU as well, so don't get your panties in a bunch

 

[Punkenjoy]

Perhaps, it's early code most likely.

But the interesting question is how do we call 1 DIMM of DDR5? It is technically dual-channel, but historically we've been calling 2 DIMMs that. How many channels will mainstream IMCs have? 4?

This is a possibility. I suspect that DDR5 will cause a lot of confusion. But on the other hands, i suppose it should be less costly to run 4 32 bit channel than 2 64 bit channel, even more when you think the voltage regulation will be on the DIMM instead of on the motherboard.

So it might be possible that these change lead to a 4 dimm/8 channel/256 bit setup. We would ahve to see altought that for now, your hypothesis of the system not detecting the DDR5 channel properly or just assuming they are 64 bit is the most probable.

The funny (or sad) thing is even with 4 channel, we could still see vendor just slapping 1 DIMM, but now they could i guess call that dual channel. That is going to be a mess for sure...

 

[Dredi]

Perhaps, it's early code most likely.

But the interesting question is how do we call 1 DIMM of DDR5? It is technically dual-channel, but historically we've been calling 2 DIMMs that. How many channels will mainstream IMCs have? 4?

We can call it 1 DIMM of DDR5
Wider than 128 bit memory controllers are unlikely, as the minimum memory capacity would be pretty large. No-one makes or has plans to introduce smaller than 16gig sticks. 64gig minimum capacity for nominal memory performance seems excessive for mainstream platforms.

 

[SL2]

Regardless, Zen2 cores will be more than fine to max out the graphical capabilities of the RDNA2 CUs in these APUs, so I don't know what everyone is whining about...

This doesn't make sense at all. APU's are used for more than pushing the integrated graphics.

People aren't going to team one of these van gogh APUs with a top of the line GPU, so Zen3 cores aren't necessary, besides Zen2 cores will keep the price down considerably so these should be ending up in some pretty graphically capable machines (mobile and desktop) at an affordable price....

What are you even talking about.. Zen 2 and Zen 3 cores are about the same size, and the same process.

 

[ncrs]

We can call it 1 DIMM of DDR5
Wider than 128 bit memory controllers are unlikely, as the minimum memory capacity would be pretty large. No-one makes or has plans to introduce smaller than 16gig sticks. 64gig minimum capacity for nominal memory performance seems excessive for mainstream platforms.

So 1 DIMM of DDR5 will be visible as "dual-channel" in CPU-Z/HWiNFO then or as single? Will 2 DIMMs be dual or quad

This doesn't make sense at all. APU's are used for more than pushing the integrated graphics.

What are you even talking about.. Zen 2 and Zen 3 cores are about the same size, and the same process.

Zen 2 refresh is on the same process, but the original is not.

 

[Dredi]

So 1 DIMM of DDR5 will be visible as "dual-channel" in CPU-Z/HWiNFO then or as single? Will 2 DIMMs be dual or quad

According to the number of channels of course. Two or four. Not sure about whether these can be dual rank too

 

[ncrs]

According to the number of channels of course. Two or four. Not sure about whether these can be dual rank too

Yeah it's going to create a lot of confusion in the future.

From what I understood from Rambus's site DDR5 can be 1, 2 or 4 rank.

Can a half-DIMM of DDR5 function as single channel tho?

 

[SL2]

Zen 2 refresh is on the same process, but the original is not.

Oh, I didn't know that. But in that case, wouldn't Van Gogh be the refreshed variant?

 

[ncrs]

Oh, I didn't know that. But in that case, wouldn't Van Gogh be the refreshed variant?

Only AMD knows that for now

 

[Tom Yum]

This doesn't make sense at all. APU's are used for more than pushing the integrated graphics.

What are you even talking about.. Zen 2 and Zen 3 cores are about the same size, and the same process.

I don't have the exact core sizes, but Zen2 CCD is 72mm2 whilst a Zen3 CCD is around 84mm2 with the same core count and cache on the same process. So Zen3 is around 15% larger than Zen2, which probably matters when 7nm supply is so tight. Still reckon Van Gogh will be Zen3 based despite this leak.

 

[SL2]

Still reckon Van Gogh will be Zen3 based despite this leak.

Me too, Zen 2 doesn't make sense. We've seen this rumor before tho.



This article suggests that it could be a mobile Xbox APU. If that's true, Zen 2 would make more sense IMO.

Microsoft handheld Xbox console rumors spring up again as AMD Van Gogh APU appears in Linux kernel code with a potential graphics boost

Linux kernel code has revealed some details about AMD’s Van Gogh Ryzen 5000 ULV mobile APU series. Apparently, the processors will offer support for 256-bit DDR5 memory, which is a step up from Renoir APUs. Unsurprisingly, the appearance of an AMD APU with greater potential graphics processing...

www.notebookcheck.net

 

[MikeMurphy]

It wouldn't surprise me if next-gen APUs have faster memory embedded on the package itself, or nearby the SOC but dedicated to the GPU functions, with system memory being a fall-back with performance penalty.

 

[SL2]

It wouldn't surprise me if next-gen APUs have faster memory embedded on the package itself, or nearby the SOC but dedicated to the GPU functions, with system memory being a fall-back with performance penalty.

It would really surprise me, as I believe IGP gaming is a niche market. For every laptop used for IGP gaming there are like what, 50 discrete GPU gaming/non gaming/office/school laptops?

 

[Dredi]

Yeah it's going to create a lot of confusion in the future.

From what I understood from Rambus's site DDR5 can be 1, 2 or 4 rank.

Can a half-DIMM of DDR5 function as single channel tho?

I don’t think you can add uneven number of channels, at least in the typical configurations.

And yes, it might create some confusion for a few months until people get the grasp of things again, but it’s still better than mislabeling stuff for legacy reasons. Most people just count memory DIMMs anyway.